module TenDiv4(BCDout,Clr,Clock);
	   
input Clock;
input Clr;
output [3:0]BCDout;

reg [3:0] BCDout;


always @(negedge Clock or negedge Clr)
   if(!Clr)
    	  BCDout <= 0;
   else if( ________________ )
           _____________;
        else
           _____________ ;


endmodule