module Freq_m( F0p8Hz,Data_out,Latch_out,Dig_sel,Clr_data,Signal_in,Clock_in );

input  Clock_in; 
________________
input  Clr_data;
input  [2:0] Dig_sel;


output Latch_out;
output [3:0]Data_out; 
output F0p8Hz;

________________ 

wire Latch;

wire [3:0] dig0,dig1,dig2,dig3,dig4,dig5,dig6;



DivStream Div1( _________ ,__________);

assign Latch = ~ F0p8Hz;
assign  Latch_out = Latch;

and AND1(sig,Latch_out,Signal_in);

TenDiv4 Div2(dig0,Clr_data,sig);
TenDiv4 Div3(dig1,Clr_data,dig0[3]);
TenDiv4 Div4(dig2,Clr_data,dig1[3]);
TenDiv4 Div5(dig3,Clr_data,dig2[3]);
TenDiv4 Div6(dig4,Clr_data,dig3[3]);
TenDiv4 Div7(dig5,Clr_data,dig4[3]);
TenDiv4 Div8(dig6,Clr_data,dig5[3]);


always @( ____________________________________________ )
   case ( Dig_sel )
      3'b000 : Data_out = dig0;
      3'b001 : Data_out = dig1;
      3'b010 : Data_out = dig2;
      3'b011 : Data_out = dig3;
      3'b100 : Data_out = dig4;
      3'b101 : Data_out = dig5;
      3'b110 : Data_out = dig6;
      3'b111 : Data_out = 0;
   endcase


endmodule