VHDL to Verilog RTL transformer

In 1.0 version ,
some functions restricted, as follows:
1: not all support "Generate" statement,totally not support "if .. Generate "
2: Comment in vhdl  may have a little chance to interrupt the transform. 
3: not support "configurate .." ,"subtype" and "package" ,please delete them at first!
4: not support the behavioral VHDL 
5: not support "record"