Host command: /eda/cadence06/IUS5.7_ins/tools/verilog/bin/verilog.exeCommand arguments:    test.v    check.vTool:	VERILOG-XL	05.70.001-p log file created Nov 25, 2008  13:19:27Tool:	VERILOG-XL	05.70.001-p   Nov 25, 2008  13:19:27Copyright (c) 1995-2004 Cadence Design Systems, Inc.  All Rights Reserved.Unpublished -- rights reserved under the copyright laws of the United States.Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc.  Reproduced with Permission.THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATIONAND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, ORREPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OFCADENCE DESIGN SYSTEMS, INC.RESTRICTED RIGHTS LEGENDUse, duplication, or disclosure by the Government is subject torestrictions as set forth in subparagraph (c)(1)(ii) of the Rights inTechnical Data and Computer Software clause at DFARS 252.227-7013 orsubparagraphs (c)(1) and (2) of Commercial Computer Software -- RestrictedRights at 48 CFR 52.227-19, as applicable.                Cadence Design Systems, Inc.                555 River Oaks Parkway                San Jose, California  95134For technical assistance please contact the Cadence Response Center at1-877-CDS-4911 or send email to support@cadence.comFor more information on Cadence's Verilog-XL product line send email totalkv@cadence.comCompiling source file "test.v"Compiling source file "check.v"Highest level modules:testL72 "test.v": $finish at simulation time 4300 simulation events (use +profile or +listcounts option to count)CPU time: 0.0 secs to compile + 0.0 secs to link + 0.1 secs in simulationEnd of Tool:	VERILOG-XL	05.70.001-p   Nov 25, 2008  13:19:27