library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.std_logic_signed.all;entity alu is       port(alu_c  :in std_logic_vector(1 downto 0);            aluin1 :in std_logic;            aluin2 :in std_logic;            aluout :out std_logic             );end alu;architecture behave of alu is       --constant aluand:std_logic_vector(1 downto 0):="01";       --constant aluor :std_logic_vector(1 downto 0):="10";       --constant aluxor:std_logic_vector(1 downto 0):="11";    begin      process(alu_c,aluin1,aluin2)        begin        case alu_c is           when "01"=>aluout<=(aluin1 and aluin2);          when "10" =>aluout<=(aluin1 or aluin2);          when "11"=>aluout<=(aluin1 xor aluin2);          when others=>null;        end case;      end process;end behave;