library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;

entity ir is
       port(memout:in std_logic_vector(15 downto 0);
               clk:in std_logic;
               rst:in std_logic;
              en_ir:in std_logic;
              instr:out std_logic_vector(15 downto 0));
end ir;

architecture one of ir is
       begin
         process(clk,rst)
           begin
           if(rst='1') then
              instr<=(others=>'0') ;
           else if(en_ir='1')then
              if(clk'event and clk='1') then
                 instr<=memout;
                 end if;
                 end if;
                 end if;
         end process;
end one;