library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;

entity muxalu1 is
       port(muxalu1_c:in std_logic;
            muxalu1_rs:in std_logic;
            --muxalu1_rt:in std_logic;
            muxalu1_out:out std_logic
            );
end muxalu1;

architecture one of muxalu1 is
  begin
    process(muxalu1_rs,muxalu1_c)
    begin
      case muxalu1_c is
          when '0'=>
                muxalu1_out<='0';
          when '1'=>
                muxalu1_out<=muxalu1_rs;
          when others=>
                null;
      end case;
    end process;
 end one;