?? pc.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;
entity pc is
port(clk:in std_logic;
rst:in std_logic;
pc_in:in std_logic_vector(15 downto 0);
pc_out:out std_logic_vector(15 downto 0));
end pc;
architecture one of pc is
begin
process(clk,rst)
begin
if(rst='1') then
pc_out<=(others=>'0');
elsif(clk'event and clk='1') then
pc_out<=pc_in;
end if;
end process;
end one;
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