?? compare.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;
entity compare is
port(comp_c:in std_logic_vector(2 downto 0);
comp_in1:in std_logic;
comp_in2:in std_logic;
comp_out:out std_logic
);
end compare;
architecture one of compare is
signal compare_temp:std_logic_vector(2 downto 0);
begin
process(comp_in1,comp_in2)
begin
if(comp_in1=comp_in2) then compare_temp<="010";
elsif (comp_in1>comp_in2) then compare_temp<="100";
else compare_temp<="001";
end if;
end process;
process(compare_temp,comp_c)
begin
if(comp_c=compare_temp) then comp_out<='1';
else comp_out<='0';
end if;
end process;
end one;
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