一段NOR FLASH 控制器的Verilog源碼，自己學習用
module flash_controller(
        input clk,
        input reset_b,
        input module_enable,

        output [127:0] string,
        output ready,
        output [20:1] a,
        output flash_ce_b,
        output we_b,
        output oe_b,

        inout [15:0] d
);

wire resetb_b = (reset_b & module_enable);

reg [19:0] adr;
reg [15:0] data;

reg t_oe_b;
reg t_we_b;
reg t_flash_ce_b;

// write test data to the whole flash
reg [15:0] received_data;
reg [15:0] polling_data;
reg [3:0] wr_state;
reg [3:0] erase_state;
reg stop_writing_0;
reg stop_writing_1;
reg stop_erasing_1;
reg stop_erasing_2;
reg [3:0] wcnt;
reg [3:0] ecnt;
//reg [18:0] wr_word_adr;
reg [19:0] wr_word_adr;
reg [15:0] wr_word_data;
reg [23:0] err_cnt;
reg [29:0] delay;
reg erase_error;
reg read_error;
wire erase_finished = &delay;
reg last_chance;
reg [7:0] wr_errors;
reg otkl;

wire ERASE1 = ~stop_erasing_1 & ~stop_writing_1 & ~stop_erasing_2 & ~stop_writing_0;
wire ERASE2 =  stop_erasing_1 &  stop_writing_1 & ~stop_erasing_2 & ~stop_writing_0;

wire WRITE1 =  stop_erasing_1 & ~stop_writing_1 & ~stop_erasing_2 & ~stop_writing_0;
wire WRITE2 =  stop_erasing_1 &  stop_writing_1 &  stop_erasing_2 & ~stop_writing_0;

always @(posedge clk) begin
        if (~resetb_b) begin
                wr_state = 0;
                erase_state = 0;
                t_oe_b <= 1;
                t_we_b <= 1;
                t_flash_ce_b <= 1;
                data <= 16'hZZZZ;
                wcnt <= 0;
                ecnt = 0;
                err_cnt    <= 0;
                stop_writing_0 <= 0;
                stop_writing_1 <= 0;
                stop_erasing_1 <= 0;
                stop_erasing_2 <= 0;
                received_data <= 0;
                polling_data <= 0;
                delay = 0;
                erase_error <= 0;
                read_error <= 0;
                last_chance <= 0;
                wr_errors = 0;
                otkl <= 1;
        end
        else begin
                if (ERASE1 | ERASE2)
                        case (erase_state)
                        0: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        adr =         (ecnt == 0) ? 19'h00555 :
                                                        (ecnt == 1) ? 19'h002AA :
                                                        (ecnt == 2) ? 19'h00555 :
                                                        (ecnt == 3) ? 19'h00555 :
                                                        (ecnt == 4) ? 19'h002AA :
                                                        (ecnt == 5) ? 19'h00555 : 19'hXXXXX;
                                        otkl <= 1;
                                        erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        1: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                t_we_b = 0;
                                t_flash_ce_b = 0;
                                data =        (ecnt == 0) ? 16'h00AA :
                                                (ecnt == 1) ? 16'h0055 :
                                                (ecnt == 2) ? 16'h0080 :
                                                (ecnt == 3) ? 16'h00AA :
                                                (ecnt == 4) ? 16'h0055 :
                                                (ecnt == 5) ? 16'h0010 : 16'hXXXX;
                                otkl <= 0;
                                erase_state = erase_state + 1'b1;
                                delay = 0;
                                end
                        end
                        2: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        3: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        t_we_b = 1;
                                        t_flash_ce_b = 1;
                                        ecnt = ecnt + 1'b1;
                                        if (ecnt < 6) erase_state = 0;
                                        else erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        4: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        otkl <= 1;
                                        ecnt = 0;
                                        erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        5: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        t_oe_b = 0;
                                        t_flash_ce_b = 0;
                                        adr = 19'h00000;
                                        erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        6: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        7: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        delay = 0;
                                        polling_data <= d;
                                        erase_state = erase_state + 1'b1;
                                end
                        end
                        8: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        t_oe_b <= 1;
                                        t_flash_ce_b <= 1;
                                        erase_state = erase_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        9: begin
                                        if (polling_data[7] == 1) begin
                                                erase_state = erase_state + 1'b1;
                                        end
                                        else begin
                                                if (last_chance) begin
                                                        erase_state = erase_state + 1'b1;
                                                        erase_error <= 1;
                                                end
                                                else
                                                        if (polling_data[5] == 1) begin
                                                                erase_state = 5;
                                                                last_chance <= 1;
                                                        end
                                                        else begin
                                                                erase_state = 5;
                                                        end
                                        end
                        end
                        10: begin
                        delay = delay + 1'b1;
                                if (delay == 10) begin
                                        if (ERASE1) begin
                                                stop_erasing_1 = 1;
                                                stop_writing_1 = 0;
                                                stop_erasing_2 = 0;
                                                stop_writing_0 = 0;
                                                wr_word_data = 16'h0001;
                                        end
                                        else if (ERASE2) begin
                                                stop_erasing_1 = 1;
                                                stop_writing_1 = 1;
                                                stop_erasing_2 = 1;
                                                stop_writing_0 = 0;
                                                wr_word_data = 16'hFFFE;
                                        end
                                        erase_state = 0;
                                        delay = 0;
                                        wr_word_adr  = 0;
                                end
                        end