fpga reference design
Offer:QuickLogic

PCI Arbiter:
Files: \APPS\pci arbiter\pci_arb.exe
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixture: TOP.TF (Verilog HDL Format)
Schematic-Based Design with Verilog Sub-Blocks
Utilization
583 of 768 logic cells, QL24x32B pASIC 1 device
480 of 672 logic cells, QL2009 pASIC 2 device
123 pins (recommended pinout available, see synthesis constraint file
TOP.SC)
Overview
This application note describes a fully PCI-compliant Master/Slave
interface. It utilizes the
PCI burst transfer mode for transfers at high speed, up to 67 MBytes per
second. Although it
is designed to interface the Seeq 80C300 Ethernet Data Link Controller
to the PCI bus, it can
be easily modified to interface with other peripherals. Data is transferred
between System
Memory and the Ethernet controller in bursts of eight using Master Mode
DMA. Internal
80C300 programming registers are mapped into host memory space and
are accessed using
slave mode.

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