# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		second_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name TOP_LEVEL_ENTITY second
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:17:55  OCTOBER 05, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "ViewDraw (Symbol)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "F:/FPGA_CHENGXU/MIAOBIAO/fenpin" -section_id eda_board_design_symbol
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VIEWDRAW -section_id eda_board_design_symbol
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name BDF_FILE second.bdf
set_global_assignment -name VHDL_FILE fenpin.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VHDL_FILE cnt_10.vhd
set_global_assignment -name VHDL_FILE xian.vhd
set_global_assignment -name VHDL_FILE cnt_12.vhd
set_global_assignment -name VHDL_FILE cnt_60.vhd
set_location_assignment PIN_67 -to reset
set_location_assignment PIN_123 -to data[0]
set_location_assignment PIN_124 -to data[1]
set_location_assignment PIN_126 -to data[2]
set_location_assignment PIN_127 -to data[3]
set_location_assignment PIN_128 -to data[4]
set_location_assignment PIN_129 -to data[5]
set_location_assignment PIN_130 -to data[6]
set_location_assignment PIN_131 -to data[7]
set_location_assignment PIN_132 -to chose[0]
set_location_assignment PIN_133 -to chose[1]
set_location_assignment PIN_139 -to chose[2]
set_location_assignment PIN_140 -to chose[3]
set_location_assignment PIN_141 -to chose[4]
set_location_assignment PIN_142 -to chose[5]
set_location_assignment PIN_143 -to chose[6]
set_location_assignment PIN_144 -to chose[7]
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_location_assignment PIN_60 -to zanting
set_location_assignment PIN_73 -to ddd
set_global_assignment -name VHDL_FILE fp2.vhd
set_location_assignment PIN_93 -to clk
set_location_assignment PIN_91 -to start