?? cnt_10.vhd.bak
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_10 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
Q :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END cnt_10;
ARCHITECTURE a OF cnt_10 IS
BEGIN
PROCESS(CLK,reset)
BEGIN
IF CLK'event AND clk='1'THEN
IF reset= '0' THEN
Q<="0000";
co<='0';
ELSIF Q="1001"THEN
co<='1';
Q<="0000";
ELSIF en='0' then
Q<=Q;
ELSE Q<=Q+1;
co<='0';
END IF;
END IF;
END PROCESS;
END a;
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