{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt_12:inst5\|QL\[0\] register xian:inst6\|data1\[3\] 58.55 MHz 17.078 ns Internal " "Info: Clock \"clk\" has Internal fmax of 58.55 MHz between source register \"cnt_12:inst5\|QL\[0\]\" and destination register \"xian:inst6\|data1\[3\]\" (period= 17.078 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.492 ns + Longest register register " "Info: + Longest register to register delay is 4.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_12:inst5\|QL\[0\] 1 REG LC_X19_Y11_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y11_N0; Fanout = 6; REG Node = 'cnt_12:inst5\|QL\[0\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QL[0] } "NODE_NAME" } } { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.114 ns) 1.368 ns xian:inst6\|Mux3~61 2 COMB LC_X19_Y12_N6 1 " "Info: 2: + IC(1.254 ns) + CELL(0.114 ns) = 1.368 ns; Loc. = LC_X19_Y12_N6; Fanout = 1; COMB Node = 'xian:inst6\|Mux3~61'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.368 ns" { cnt_12:inst5|QL[0] xian:inst6|Mux3~61 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.114 ns) 1.907 ns xian:inst6\|Mux3~62 3 COMB LC_X19_Y12_N0 1 " "Info: 3: + IC(0.425 ns) + CELL(0.114 ns) = 1.907 ns; Loc. = LC_X19_Y12_N0; Fanout = 1; COMB Node = 'xian:inst6\|Mux3~62'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.539 ns" { xian:inst6|Mux3~61 xian:inst6|Mux3~62 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.114 ns) 2.455 ns xian:inst6\|Mux3~65 4 COMB LC_X19_Y12_N5 7 " "Info: 4: + IC(0.434 ns) + CELL(0.114 ns) = 2.455 ns; Loc. = LC_X19_Y12_N5; Fanout = 7; COMB Node = 'xian:inst6\|Mux3~65'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.548 ns" { xian:inst6|Mux3~62 xian:inst6|Mux3~65 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.292 ns) 3.958 ns xian:inst6\|Mux17~52 5 COMB LC_X18_Y12_N0 1 " "Info: 5: + IC(1.211 ns) + CELL(0.292 ns) = 3.958 ns; Loc. = LC_X18_Y12_N0; Fanout = 1; COMB Node = 'xian:inst6\|Mux17~52'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.503 ns" { xian:inst6|Mux3~65 xian:inst6|Mux17~52 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.420 ns) + CELL(0.114 ns) 4.492 ns xian:inst6\|data1\[3\] 6 REG LC_X18_Y12_N4 1 " "Info: 6: + IC(0.420 ns) + CELL(0.114 ns) = 4.492 ns; Loc. = LC_X18_Y12_N4; Fanout = 1; REG Node = 'xian:inst6\|data1\[3\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.534 ns" { xian:inst6|Mux17~52 xian:inst6|data1[3] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.748 ns ( 16.65 % ) " "Info: Total cell delay = 0.748 ns ( 16.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.744 ns ( 83.35 % ) " "Info: Total interconnect delay = 3.744 ns ( 83.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.492 ns" { cnt_12:inst5|QL[0] xian:inst6|Mux3~61 xian:inst6|Mux3~62 xian:inst6|Mux3~65 xian:inst6|Mux17~52 xian:inst6|data1[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "4.492 ns" { cnt_12:inst5|QL[0] {} xian:inst6|Mux3~61 {} xian:inst6|Mux3~62 {} xian:inst6|Mux3~65 {} xian:inst6|Mux17~52 {} xian:inst6|data1[3] {} } { 0.000ns 1.254ns 0.425ns 0.434ns 1.211ns 0.420ns } { 0.000ns 0.114ns 0.114ns 0.114ns 0.292ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.995 ns - Smallest " "Info: - Smallest clock skew is -1.995 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 28.637 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 28.637 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 37 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 37; CLK Node = 'clk'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns fenpin:inst\|clk1 2 REG LC_X23_Y8_N6 5 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'fenpin:inst\|clk1'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { clk fenpin:inst|clk1 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.478 ns) + CELL(0.935 ns) 8.419 ns cnt_10:inst1\|co 3 REG LC_X19_Y10_N0 6 " "Info: 3: + IC(4.478 ns) + CELL(0.935 ns) = 8.419 ns; Loc. = LC_X19_Y10_N0; Fanout = 6; REG Node = 'cnt_10:inst1\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.413 ns" { fenpin:inst|clk1 cnt_10:inst1|co } "NODE_NAME" } } { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.768 ns) + CELL(0.935 ns) 14.122 ns cnt_10:inst2\|co 4 REG LC_X15_Y6_N9 10 " "Info: 4: + IC(4.768 ns) + CELL(0.935 ns) = 14.122 ns; Loc. = LC_X15_Y6_N9; Fanout = 10; REG Node = 'cnt_10:inst2\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.703 ns" { cnt_10:inst1|co cnt_10:inst2|co } "NODE_NAME" } } { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.348 ns) + CELL(0.935 ns) 19.405 ns cnt_60:inst3\|QH\[3\] 5 REG LC_X20_Y11_N7 3 " "Info: 5: + IC(4.348 ns) + CELL(0.935 ns) = 19.405 ns; Loc. = LC_X20_Y11_N7; Fanout = 3; REG Node = 'cnt_60:inst3\|QH\[3\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { cnt_10:inst2|co cnt_60:inst3|QH[3] } "NODE_NAME" } } { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 19.783 ns xian:inst6\|Mux0~47 6 COMB LC_X20_Y11_N7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.378 ns) = 19.783 ns; Loc. = LC_X20_Y11_N7; Fanout = 1; COMB Node = 'xian:inst6\|Mux0~47'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.378 ns" { cnt_60:inst3|QH[3] xian:inst6|Mux0~47 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.442 ns) 21.375 ns xian:inst6\|Mux0~48 7 COMB LC_X19_Y12_N9 5 " "Info: 7: + IC(1.150 ns) + CELL(0.442 ns) = 21.375 ns; Loc. = LC_X19_Y12_N9; Fanout = 5; COMB Node = 'xian:inst6\|Mux0~48'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { xian:inst6|Mux0~47 xian:inst6|Mux0~48 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.114 ns) 22.196 ns xian:inst6\|Mux22~55 8 COMB LC_X20_Y12_N2 7 " "Info: 8: + IC(0.707 ns) + CELL(0.114 ns) = 22.196 ns; Loc. = LC_X20_Y12_N2; Fanout = 7; COMB Node = 'xian:inst6\|Mux22~55'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.821 ns" { xian:inst6|Mux0~48 xian:inst6|Mux22~55 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.149 ns) + CELL(0.292 ns) 28.637 ns xian:inst6\|data1\[3\] 9 REG LC_X18_Y12_N4 1 " "Info: 9: + IC(6.149 ns) + CELL(0.292 ns) = 28.637 ns; Loc. = LC_X18_Y12_N4; Fanout = 1; REG Node = 'xian:inst6\|data1\[3\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.441 ns" { xian:inst6|Mux22~55 xian:inst6|data1[3] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.435 ns ( 22.47 % ) " "Info: Total cell delay = 6.435 ns ( 22.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "22.202 ns ( 77.53 % ) " "Info: Total interconnect delay = 22.202 ns ( 77.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "28.637 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|QH[3] xian:inst6|Mux0~47 xian:inst6|Mux0~48 xian:inst6|Mux22~55 xian:inst6|data1[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "28.637 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|QH[3] {} xian:inst6|Mux0~47 {} xian:inst6|Mux0~48 {} xian:inst6|Mux22~55 {} xian:inst6|data1[3] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 0.000ns 1.150ns 0.707ns 6.149ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.378ns 0.442ns 0.114ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 30.632 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 30.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 37 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 37; CLK Node = 'clk'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns fenpin:inst\|clk1 2 REG LC_X23_Y8_N6 5 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'fenpin:inst\|clk1'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { clk fenpin:inst|clk1 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.478 ns) + CELL(0.935 ns) 8.419 ns cnt_10:inst1\|co 3 REG LC_X19_Y10_N0 6 " "Info: 3: + IC(4.478 ns) + CELL(0.935 ns) = 8.419 ns; Loc. = LC_X19_Y10_N0; Fanout = 6; REG Node = 'cnt_10:inst1\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.413 ns" { fenpin:inst|clk1 cnt_10:inst1|co } "NODE_NAME" } } { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.768 ns) + CELL(0.935 ns) 14.122 ns cnt_10:inst2\|co 4 REG LC_X15_Y6_N9 10 " "Info: 4: + IC(4.768 ns) + CELL(0.935 ns) = 14.122 ns; Loc. = LC_X15_Y6_N9; Fanout = 10; REG Node = 'cnt_10:inst2\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.703 ns" { cnt_10:inst1|co cnt_10:inst2|co } "NODE_NAME" } } { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.348 ns) + CELL(0.935 ns) 19.405 ns cnt_60:inst3\|co 5 REG LC_X15_Y6_N2 10 " "Info: 5: + IC(4.348 ns) + CELL(0.935 ns) = 19.405 ns; Loc. = LC_X15_Y6_N2; Fanout = 10; REG Node = 'cnt_60:inst3\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { cnt_10:inst2|co cnt_60:inst3|co } "NODE_NAME" } } { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.338 ns) + CELL(0.935 ns) 24.678 ns cnt_60:inst4\|co 6 REG LC_X18_Y11_N9 9 " "Info: 6: + IC(4.338 ns) + CELL(0.935 ns) = 24.678 ns; Loc. = LC_X18_Y11_N9; Fanout = 9; REG Node = 'cnt_60:inst4\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.273 ns" { cnt_60:inst3|co cnt_60:inst4|co } "NODE_NAME" } } { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.243 ns) + CELL(0.711 ns) 30.632 ns cnt_12:inst5\|QL\[0\] 7 REG LC_X19_Y11_N0 6 " "Info: 7: + IC(5.243 ns) + CELL(0.711 ns) = 30.632 ns; Loc. = LC_X19_Y11_N0; Fanout = 6; REG Node = 'cnt_12:inst5\|QL\[0\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.954 ns" { cnt_60:inst4|co cnt_12:inst5|QL[0] } "NODE_NAME" } } { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.855 ns ( 22.38 % ) " "Info: Total cell delay = 6.855 ns ( 22.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "23.777 ns ( 77.62 % ) " "Info: Total interconnect delay = 23.777 ns ( 77.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "30.632 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|co cnt_60:inst4|co cnt_12:inst5|QL[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "30.632 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|co {} cnt_60:inst4|co {} cnt_12:inst5|QL[0] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 4.338ns 5.243ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "28.637 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|QH[3] xian:inst6|Mux0~47 xian:inst6|Mux0~48 xian:inst6|Mux22~55 xian:inst6|data1[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "28.637 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|QH[3] {} xian:inst6|Mux0~47 {} xian:inst6|Mux0~48 {} xian:inst6|Mux22~55 {} xian:inst6|data1[3] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 0.000ns 1.150ns 0.707ns 6.149ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.378ns 0.442ns 0.114ns 0.292ns } "" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "30.632 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|co cnt_60:inst4|co cnt_12:inst5|QL[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "30.632 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|co {} cnt_60:inst4|co {} cnt_12:inst5|QL[0] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 4.338ns 5.243ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.828 ns + " "Info: + Micro setup delay of destination is 1.828 ns" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.492 ns" { cnt_12:inst5|QL[0] xian:inst6|Mux3~61 xian:inst6|Mux3~62 xian:inst6|Mux3~65 xian:inst6|Mux17~52 xian:inst6|data1[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "4.492 ns" { cnt_12:inst5|QL[0] {} xian:inst6|Mux3~61 {} xian:inst6|Mux3~62 {} xian:inst6|Mux3~65 {} xian:inst6|Mux17~52 {} xian:inst6|data1[3] {} } { 0.000ns 1.254ns 0.425ns 0.434ns 1.211ns 0.420ns } { 0.000ns 0.114ns 0.114ns 0.114ns 0.292ns 0.114ns } "" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "28.637 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|QH[3] xian:inst6|Mux0~47 xian:inst6|Mux0~48 xian:inst6|Mux22~55 xian:inst6|data1[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "28.637 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|QH[3] {} xian:inst6|Mux0~47 {} xian:inst6|Mux0~48 {} xian:inst6|Mux22~55 {} xian:inst6|data1[3] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 0.000ns 1.150ns 0.707ns 6.149ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.378ns 0.442ns 0.114ns 0.292ns } "" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "30.632 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|co cnt_60:inst4|co cnt_12:inst5|QL[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "30.632 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|co {} cnt_60:inst4|co {} cnt_12:inst5|QL[0] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 4.338ns 5.243ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}