LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY counter IS
	PORT (Hold, Reset, Clk 	: IN 	  STD_LOGIC;			
		  Num 				: Buffer  Integer Range 0 To 49 );
END counter;

ARCHITECTURE counter_architecture OF counter IS
BEGIN
	PROCESS (reset, clk, hold)
	BEGIN
		If   (reset='1') 	Then	num <= 0;	-- 系統(tǒng)啟動，開始計數(shù)
		Else 
	   		If  ( rising_edge(clk) )   Then
		  		If    ( hold='1') Then 
					num <= num;				-- 出現(xiàn)特殊情況，暫停計數(shù)
		  		Elsif ( num<49 )  Then
			 		num <= num+1;			-- 每個時鐘周期，計數(shù)加1
		  		Elsif ( num=49 )  Then
			 		num <= 0;				-- 計數(shù)規(guī)零，重新計數(shù)
		  		End If;
	 		End If;
	 	End If; 
	END PROCESS;
END counter_architecture;