module    TestBench;reg    [10:0]    Vmem   [1: 0] ; reg     [2: 0]      A , B;  reg     Cin;wire        [2:0] Sum; wire        Cout; reg     [2: 0]   Sum_Ex; reg              Cout_Ex; reg [2:0]   counter;//被測(cè)試驗(yàn)證的模塊實(shí)例。Adder3Bit    F1  (A, B, Cin, Sum, Cout ) ;initial  begin        $readmemb ("test.vec", Vmem );         for (counter=0; counter<=1; counter = counter+ 1)         begin              {A, B, Cin, Sum_Ex, Cout_Ex}= Vmem [counter] ;                  #5; //延遲5個(gè)時(shí)間單位等待電路穩(wěn)定。       if ( (Sum!=Sum_Ex) || (Cout!=Cout_Ex) )        $display ("****Mismatch on vector: %b *****", Vmem[counter] ) ;       else          $display ("No mismatch on vector :%b", Vmem[counter] ) ;        endendendmodule