----------------------------------------------------------------------------------  File Name: cdc508.vhd----------------------------------------------------------------------------------  Copyright (C) 2002-2003 Free Model Foundry; http://www.FreeModelFoundry.com/-- --  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.-- --  MODIFICATION HISTORY:-- --  version: |  author:  | mod date: | changes made:--    V1.0    R. Munden    02 Dec 05   Initial release--    V1.1    R. Munden    02 Jan 06   modified use of _nwv to satisfy ncvhdl-- ----------------------------------------------------------------------------------  PART DESCRIPTION:-- --  Library:    CLOCK--  Technology: CMOS--  Part:       CDC508-- --  Description: PLL Clock Driver with 3-State Outputs--------------------------------------------------------------------------------LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;                USE IEEE.VITAL_timing.ALL;                USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;    USE FMF.gen_utils.ALL;                USE FMF.ff_package.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cdc508 IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_FBIN                : VitalDelayType01 := VitalZeroDelay01;        tipd_CLKIN               : VitalDelayType01 := VitalZeroDelay01;        tipd_S1                  : VitalDelayType01 := VitalZeroDelay01;        tipd_S2                  : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays        tpd_CLKIN_Y1A            : VitalDelayType01 := UnitDelay01;        -- tperiod_min: minimum clock period = 1/max freq        tperiod_FBIN_posedge     : VitalDelayType := UnitDelay;        -- generic control parameters        InstancePath        : STRING    := DefaultInstancePath;        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;        MsgOn               : BOOLEAN   := DefaultMsgOn;        XOn                 : BOOLEAN   := DefaultXon;        -- For FMF SDF technology file usage        TimingModel         : STRING    := DefaultTimingModel    );    PORT (        FBIN            : IN    std_logic := 'U';        CLKIN           : IN    std_logic := 'U';        S1              : IN    std_logic := 'U';        S2              : IN    std_logic := 'U';        Y1A             : OUT   std_logic := 'U';        Y1B             : OUT   std_logic := 'U';        Y1C             : OUT   std_logic := 'U';        Y1D             : OUT   std_logic := 'U';        Y2A             : OUT   std_logic := 'U';        Y2B             : OUT   std_logic := 'U';        Y2C             : OUT   std_logic := 'U';        Y2D             : OUT   std_logic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of cdc508 : ENTITY IS TRUE;END cdc508;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cdc508 IS    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;    SIGNAL FBIN_ipd            : std_ulogic := 'U';    SIGNAL CLKIN_ipd           : std_ulogic := 'U';    SIGNAL S1_ipd              : std_ulogic := 'U';    SIGNAL S2_ipd              : std_ulogic := 'U';    SIGNAL pll_out             : std_ulogic := '1';    SIGNAL tmux_out            : std_ulogic := 'U';    SIGNAL rst_int             : std_ulogic := '0';      SIGNAL Y1                  : std_ulogic := 'U';    SIGNAL Y2                  : std_ulogic := 'U';    SIGNAL vco_lock            : boolean;    SIGNAL pll_delay           : time := 0 ns;    SIGNAL half_per            : time := 6 ns;    SIGNAL S1_nwv              : X01 := 'X';    SIGNAL S2_nwv              : X01 := 'X';    SIGNAL Violation           : X01 := '0';BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1 : VitalWireDelay (FBIN_ipd, FBIN, tipd_FBIN);        w_2 : VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN);        w_3 : VitalWireDelay (S1_ipd, S1, tipd_S1);        w_4 : VitalWireDelay (S2_ipd, S2, tipd_S2);    END BLOCK;    S1_nwv <= to_X01(S1_ipd);    S2_nwv <= to_X01(S2_ipd);    Y1A <= Y1;    Y1B <= Y1;    Y1C <= Y1;    Y1D <= Y1;    Y2A <= Y2;    Y2B <= Y2;    Y2C <= Y2;    Y2D <= Y2;    ----------------------------------------------------------------------------    -- ADJ Process    ----------------------------------------------------------------------------    ADJ : PROCESS (FBIN_ipd, CLKIN_ipd)        VARIABLE fbi_period   : time := 0 ns;        VARIABLE clk_period   : time := 0 ns;        VARIABLE prev_clk     : time := 0 ns;        VARIABLE prev_fbi     : time := 0 ns;        VARIABLE toggle1      : boolean;        VARIABLE toggle2      : boolean;        -- Timing Check Variables        VARIABLE Pviol_FBIN     : X01 := '0';        VARIABLE PD_FBIN        : VitalPeriodDataType := VitalPeriodDataInit;    BEGIN        ------------------------------------------------------------------------        -- Timing Check Section        ------------------------------------------------------------------------        IF (TimingChecksOn) THEN             VitalPeriodPulseCheck (                TestSignal      => FBIN_ipd,                TestSignalName  => "FBIN_ipd",                Period          => tperiod_FBIN_posedge,                CheckEnabled    => TRUE,                HeaderMsg       => InstancePath & "/cdc508",                PeriodData      => PD_FBIN,                XOn             => XOn,                MsgOn           => MsgOn,                Violation       => Pviol_FBIN            );        END IF;        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------        Violation <= Pviol_FBIN;        IF rising_edge(CLKIN_ipd) THEN            clk_period := NOW - prev_clk;            prev_clk := NOW;            IF FBIN_ipd = 'X' THEN               rst_int <= '1', '0' AFTER 5 ns;            END IF;        END IF;        IF (FBIN_ipd'event AND FBIN_ipd = '0') THEN            rst_int <= '0';            fbi_period := NOW - prev_fbi;            prev_fbi := NOW;            IF toggle1 AND toggle2 THEN                IF fbi_period > clk_period THEN                    half_per <= half_per - 50 ps;                    vco_lock <= false;                ELSIF fbi_period < clk_period THEN                    half_per <= half_per + 60 ps;                    vco_lock <= false;                ELSE                    vco_lock <= true;                END IF;            END IF;            toggle1 := not toggle1;            IF toggle1 THEN                toggle2 := not toggle2;            ELSE                pll_delay <= 0 ps;            END IF;        END IF;        IF rising_edge(FBIN_ipd) AND vco_lock AND toggle1 AND toggle2 THEN            IF (prev_clk + 150 ps) < NOW THEN                IF pll_delay < clk_period THEN                    pll_delay <= pll_delay - 60 ps;                END IF;            END IF;        END IF;    END PROCESS ADJ;    ----------------------------------------------------------------------------    -- PLL Process    ----------------------------------------------------------------------------    PLL : PROCESS (pll_out, CLKIN_ipd, S1_nwv, S2_nwv)    BEGIN        IF S1_nwv = '0' AND S2_nwv = '1' THEN            pll_out <= CLKIN_ipd;        ELSE            pll_out <= TRANSPORT not pll_out AFTER pll_delay + half_per;        END IF;    END PROCESS PLL;    ----------------------------------------------------------------------------    -- OUTP Process    ----------------------------------------------------------------------------    OUTP : PROCESS (S1_ipd, S2_ipd, pll_out, CLKIN_ipd)        -- Functionality Results Variables        VARIABLE Y1_zd              : std_ulogic;        VARIABLE Y2_zd              : std_ulogic;        -- Output Glitch Detection Variables        VARIABLE Y1_GlitchData      : VitalGlitchDataType;        VARIABLE Y2_GlitchData      : VitalGlitchDataType;    BEGIN        Y1_zd := VitalBUFIF1 (data => pll_out, enable => (S1_ipd OR S2_ipd));        Y2_zd := VitalBUFIF1 (data => pll_out, enable => S2_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01Z (            OutSignal       => Y1,            OutSignalName   => "Y1",            OutTemp         => Y1_zd,            GlitchData      => Y1_GlitchData,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime  => pll_out'LAST_EVENT,                      PathDelay        => VitalZeroDelay01Z,                      PathCondition    => TRUE),                1 => (InputChangeTime  => CLKIN_ipd'LAST_EVENT,                      PathDelay        => VitalExtendToFillDelay(tpd_CLKIN_Y1A),                      PathCondition    => (S1_nwv = '1' OR S2_nwv = '1'))            )        );        VitalPathDelay01Z (            OutSignal       => Y2,            OutSignalName   => "Y2",            OutTemp         => Y2_zd,            GlitchData      => Y2_GlitchData,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => pll_out'LAST_EVENT,                      PathDelay         => VitalZeroDelay01Z,                      PathCondition     => TRUE),                1 => (InputChangeTime   => CLKIN_ipd'LAST_EVENT,                      PathDelay         => VitalExtendToFillDelay(tpd_CLKIN_Y1A),                      PathCondition     => (S2_nwv = '1'))            )        );    END PROCESS OUTP;END vhdl_behavioral;