----------------------------------------------------------------------------------  File name: cgs2535.vhd----------------------------------------------------------------------------------  Copyright (C) 2000 Free Model Foundry; http://www.FreeModelFoundry.com/----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.----  MODIFICATION HISTORY:----  version: |  author:  | mod date: | changes made:--    V1.0     R. Steele   00 NOV 13   Conformed to style guide---------------------------------------------------------------------------------  PART DESCRIPTION:----  Library:        CLOCK--  Technology:     Not ECL--  Part:           CGS2535----  Description:    Quad 1 to 4 clock distributor ----------------------------------------------------------------------------------LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;                 USE IEEE.VITAL_timing.ALL;                 USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;     USE FMF.gen_utils.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cgs2535 IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_A              : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays        tpd_A_Y0            : VitalDelayType01 := UnitDelay01;        -- generic control parameters        MsgOn               : BOOLEAN  := DefaultMsgOn;        XOn                 : BOOLEAN  := DefaultXOn;        InstancePath        : STRING   := DefaultInstancePath;        -- For FMF SDF techonology file usage        TimingModel         : STRING   := DefaultTimingModel    );    PORT (        A           : IN    std_ulogic := 'U';        Y0          : OUT   std_ulogic := 'U';        Y1          : OUT   std_ulogic := 'U';        Y2          : OUT   std_ulogic := 'U';        Y3          : OUT   std_ulogic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of cgs2535 : ENTITY IS TRUE;END cgs2535;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cgs2535 IS    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;    SIGNAL A_ipd        : std_ulogic := 'X';    SIGNAL Yint         : std_ulogic := 'X';BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1: VitalWireDelay (A_ipd, A, tipd_A);    END BLOCK;    ----------------------------------------------------------------------------    -- Concurrent Procedures    ----------------------------------------------------------------------------    a_0: VitalBUF (q => Y0, a => Yint);    a_1: VitalBUF (q => Y1, a => Yint);    a_2: VitalBUF (q => Y2, a => Yint);    a_3: VitalBUF (q => Y3, a => Yint);        ----------------------------------------------------------------------------        -- VITALBehavior Process    ----------------------------------------------------------------------------   VITALBehavior : PROCESS(A_ipd)        -- Functionality Results Variables        VARIABLE Y_zd        : std_ulogic := 'X';        -- Output Glitch Detection Variables        VARIABLE Y_GlitchData : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------        Y_zd := VitalBUF(data=> A_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       => Yint,            OutSignalName   => "Y",            OutTemp         => Y_zd,            GlitchData      => Y_GlitchData,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_Y0,                      PathCondition     => TRUE)           )        );    END PROCESS;END vhdl_behavioral;