--------------------------------------------------------------------------------- File Name: sy89876l.vhd--------------------------------------------------------------------------------- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com/---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- MODIFICATION HISTORY:---- version: |    author:      | mod date:  | changes made:--  V1.0       V.Ljubisavljevic   05 Jun 02    Initial release--------------------------------------------------------------------------------- PART DESCRIPTION:---- Library:     CLOCK-- Technology:  LVDS-- Part:        SY89876L-- Description: Programmable clock divider--------------------------------------------------------------------------------- Because of this changes, some model functionalities are ignored.-- VT pin is now don't care.--------------------------------------------------------------------------------- SIMULATION RESOLUTION MUST BE 1 ps-------------------------------------------------------------------------------LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;                USE IEEE.VITAL_timing.ALL;                USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;    USE FMF.gen_utils.ALL;                USE FMF.conversions.ALL;--------------------------------------------------------------------------------- ENTITY DECLARATION-------------------------------------------------------------------------------ENTITY sy89876l IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_VIN        : VitalDelayType01  := VitalZeroDelay01;        tipd_VINNeg     : VitalDelayType01  := VitalZeroDelay01;        tipd_VT         : VitalDelayType01  := VitalZeroDelay01;        tipd_S0         : VitalDelayType01  := VitalZeroDelay01;        tipd_S1         : VitalDelayType01  := VitalZeroDelay01;        tipd_S2         : VitalDelayType01  := VitalZeroDelay01;        tipd_RESETNeg   : VitalDelayType01  := VitalZeroDelay01;        tpd_VIN_Q0      : VitalDelayType01 := UnitDelay01;        thold_VIN_RESETNeg : VitalDelayType := UnitDelay;        -- tperiod_min: minimum clock period = 1/max freq        tperiod_VIN     : VitalDelayType := UnitDelay;        -- tdevice: Reset recovery time        tdevice_TRESET  : VitalDelayType := 600 ps;        -- generic control parameters        InstancePath    : STRING  := DefaultInstancePath;        TimingChecksOn  : BOOLEAN := DefaultTimingChecks;        MsgOn           : BOOLEAN := DefaultMsgOn;        XOn             : BOOLEAN := DefaultXon;        -- For FMF SDF technology file usage        TimingModel     : STRING  := DefaultTimingModel    );    PORT (        VIN             : IN  std_ulogic := 'U';        VINNeg          : IN  std_ulogic := 'U';        VT              : IN  std_ulogic := 'U';        S0              : IN  std_ulogic := 'U';        S1              : IN  std_ulogic := 'U';        S2              : IN  std_ulogic := 'U';        RESETNeg        : IN  std_ulogic := 'U';        Q0              : OUT std_ulogic := 'U';        Q0Neg           : OUT std_ulogic := 'U';        Q1              : OUT std_ulogic := 'U';        Q1Neg           : OUT std_ulogic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of sy89876l : ENTITY IS TRUE;END sy89876l;--------------------------------------------------------------------------------- ARCHITECTURE DECLARATION-------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of sy89876l IS    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;    CONSTANT partID       : STRING     := "sy89876l";    SIGNAL   VIN_ipd      : std_ulogic := 'U';    SIGNAL   VINNeg_ipd   : std_ulogic := 'U';    SIGNAL   VT_ipd       : std_ulogic := 'U';    SIGNAL   S0_ipd       : std_ulogic := 'U';    SIGNAL   S1_ipd       : std_ulogic := 'U';    SIGNAL   S2_ipd       : std_ulogic := 'U';    SIGNAL   RESETNeg_ipd : std_ulogic := 'U';    SIGNAL TR_in          : std_ulogic := '0';    SIGNAL TR_out         : std_ulogic := '0';    SIGNAL TRESET_in      : std_ulogic := '0';    SIGNAL TRESET_out     : std_ulogic := '0';BEGIN    ---------------------------------------------------------------------------    -- Internal delays    ---------------------------------------------------------------------------    -- Artificial VITAL primitives to incorporate internal delays    TRESET : VitalBUF(TRESET_out,TRESET_in,(UnitDelay,tdevice_TRESET));    ---------------------------------------------------------------------------    -- Wire Delays    ---------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1  : VitalWireDelay(VIN_ipd,VIN,tipd_VIN);        w_2  : VitalWireDelay(VINNeg_ipd,VINNeg,tipd_VINNeg);        w_3  : VitalWireDelay (S0_ipd, S0, tipd_S0);        w_4  : VitalWireDelay (S1_ipd, S1, tipd_S1);        w_5  : VitalWireDelay (S2_ipd, S2, tipd_S2);        w_6  : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg);        w_7  : VitalWireDelay(VT_ipd,VT,tipd_VT);    END BLOCK;    Behavior : BLOCK        PORT (            VIN       : IN  std_ulogic := 'U';            VINNeg    : IN  std_ulogic := 'U';            VT        : IN  std_ulogic := 'U';            S0        : IN  std_ulogic := 'U';            S1        : IN  std_ulogic := 'U';            S2        : IN  std_ulogic := 'U';            RESETNeg  : IN  std_ulogic := 'U';            Q0        : OUT std_ulogic := 'U';            Q0Neg     : OUT std_ulogic := 'U';            Q1        : OUT std_ulogic := 'U';            Q1Neg     : OUT std_ulogic := 'U'            );        PORT MAP (            VIN          => VIN_ipd,            VINNeg       => VINNeg_ipd,            VT           => VT,            S0           => S0_ipd,            S1           => S1_ipd,            S2           => S2_ipd,            RESETNeg     => RESETNeg_ipd,            Q0           => Q0,            Q0Neg        => Q0Neg,            Q1           => Q1,            Q1Neg        => Q1Neg            );        -- Powerup        SIGNAL PoweredUp     : std_logic := '0';        SIGNAL Qout_zd  : std_ulogic := 'U';        SIGNAL Qout_tmp : std_logic  := 'U';        SIGNAL divisor  : NATURAL    := 1;        SIGNAL viol     : X01        := '0';        SIGNAL RST_ACT  : BOOLEAN    := FALSE;        SIGNAL VINReg   : std_ulogic := 'U';    BEGIN    PoweredUp <= '1' AFTER 10 ps;    TRESET_in <= NOT RESETNeg;    RESET_P: PROCESS (TRESET_out) IS    BEGIN  -- PROCESS RESET_P        IF falling_edge(TRESET_out) THEN            RST_ACT <= FALSE;        ELSIF rising_edge(TRESET_out) THEN            RST_ACT <= TRUE;        END IF;    END PROCESS RESET_P;    ---------------------------------------------------------------------------    -- VITAL Timing Checks Procedures    ---------------------------------------------------------------------------    VITALTimingCheck : PROCESS (VIN, VINNeg, RESETNeg)        VARIABLE Tviol_VIN_RESETNeg : X01                 := '0';           VARIABLE TD_VIN_RESETNeg    : VitalTimingDataType;        VARIABLE Pviol_VIN          : X01                 := '0';        VARIABLE PD_VIN             : VitalPeriodDataType :=            VitalPeriodDataInit;        VARIABLE Violation          : X01 := '0';        VARIABLE PrevData : std_logic_vector(0 TO 1);        VARIABLE Vreg : std_ulogic := 'U';    BEGIN        IF TimingChecksOn THEN            -- Setup/Hold Checks            Violation := '0';            VitalSetupHoldCheck (                    TestSignal     => VIN,                    TestSignalName => "VIN",                    RefSignal      => RESETNeg,                    RefSignalName  => "RESETNeg",                    HoldLow        => thold_VIN_RESETNeg,                    HoldHigh       => thold_VIN_RESETNeg,                    CheckEnabled   => TRUE,                    RefTransition  => '/',                    HeaderMsg      => InstancePath & partID,                    TimingData     => TD_VIN_RESETNeg,                    XOn            => XOn,                    MsgOn          => MsgOn,                    Violation      => Tviol_VIN_RESETNeg                    );            VitalPeriodPulseCheck (                    TestSignal     => VIN,                    TestSignalName => "VIN",                    Period         => tperiod_VIN,                    CheckEnabled   => TRUE,                    HeaderMsg      => InstancePath & partID,                    PeriodData     => PD_VIN,                    XOn            => XOn,                    MsgOn          => MsgOn,                    Violation      => Pviol_VIN                    );            Violation := Tviol_VIN_RESETNeg OR Pviol_VIN;            ASSERT Violation = '0'                REPORT InstancePath & partID & ": simulation may be" &                       " inaccurate due to timing violations"                SEVERITY Warning;            viol <= violation;        END IF;        VitalStateTable(            StateTable => diff_rec_tab,            DataIn => (VIN, VINNeg),            Result => Vreg,            PreviousDataIn => PrevData            );        VINReg <= Vreg;    END PROCESS VITALTimingCheck;    -----------------------------------------------------------------------    -- Divider Process    -----------------------------------------------------------------------    DIVVIN : PROCESS (VINReg)            VARIABLE    div_in  : natural;            VARIABLE    div_cnt : natural;            VARIABLE    first   : BOOLEAN := true;    BEGIN        div_in := divisor/2;        IF (RESETNeg = '1'  AND divisor > 1) AND rising_edge(VINReg) THEN            IF first THEN                Qout_zd <= VINReg;                first := false;                div_cnt := div_cnt + 1;            ELSIF div_cnt < div_in THEN                div_cnt := div_cnt + 1;            ELSE                div_cnt := 1;                Qout_zd <= NOT(Qout_zd);            END IF;        ELSIF RESETNeg = '1' AND divisor = 1 THEN            Qout_zd <= VINReg;        ELSIF RESETNeg = '0' THEN            first := true;            div_cnt := 0;            Qout_zd <= '0';        END IF;    END PROCESS DIVVIN;    --------------------------------------------------    -- generated divisor of input frequency    --------------------------------------------------    divider : PROCESS(S0, S1, S2, RESETNeg, VINReg)    VARIABLE s_input : std_logic_vector(2 DOWNTO 0);    BEGIN        s_input := S2 & S1 & S0;        IF RESETNeg = '1' AND PoweredUp = '1' THEN            CASE s_input IS                WHEN "100" => divisor <= 2;                WHEN "101" => divisor <= 4;                WHEN "110" => divisor <= 8;                WHEN "111" => divisor <= 16;                WHEN others => divisor <= 1;            END CASE;        END IF;    END PROCESS divider;    ------------------------------------------------    -- path delay    ------------------------------------------------    Q0_output: PROCESS(Qout_zd)        VARIABLE Q_GlitchData : VitalGlitchDataType;    BEGIN        VitalPathDelay01(            OutSignal     => Qout_tmp,            OutSignalName => "Qout_tmp",            OutTemp       => Qout_zd,            Mode          => VitalTransport,            GlitchData    => Q_GlitchData,            Paths         => (                0 => (InputChangeTime   => Qout_zd'LAST_EVENT,                      PathDelay         => tpd_VIN_Q0,                      PathCondition     => NOT RST_ACT))            );    END PROCESS Q0_output;    ------------------------------------------------------------------------    -- Output generation    ------------------------------------------------------------------------    Q0 <= Qout_tmp;    Q0Neg <= NOT Qout_tmp;    Q1 <= Qout_tmp;    Q1Neg <= NOT Qout_tmp;    END BLOCK;END vhdl_behavioral;