----------------------------------------------------------------------------------  File Name: cdc328a.vhd----------------------------------------------------------------------------------  Copyright (C) 1998 Free Model Foundry http://www.FreeModelFoundry.com/-- --  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.-- --  MODIFICATION HISTORY:-- --  version: |  author:  | mod date: | changes made:--    V1.0    R. Munden    98 APR 29   Initial release-- ----------------------------------------------------------------------------------  PART DESCRIPTION:-- --  Library:    CLOCK--  Technology: TTL--  Part:       CDC328-- --  Desciption: Clock driver with selectable polarity--------------------------------------------------------------------------------LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;                USE IEEE.VITAL_timing.ALL;                USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;    USE FMF.gen_utils.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cdc328a IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_TC1                 : VitalDelayType01 := VitalZeroDelay01;        tipd_TC2                 : VitalDelayType01 := VitalZeroDelay01;        tipd_TC3                 : VitalDelayType01 := VitalZeroDelay01;        tipd_TC4                 : VitalDelayType01 := VitalZeroDelay01;        tipd_A                   : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays        tpd_TC4_N4Y              : VitalDelayType01 := UnitDelay01;        tpd_A_N4Y                : VitalDelayType01 := UnitDelay01;        -- generic control parameters        InstancePath        : STRING    := DefaultInstancePath;        MsgOn               : BOOLEAN   := DefaultMsgOn;        XOn                 : BOOLEAN   := DefaultXon;        -- For FMF SDF technology file usage        TimingModel         : STRING    := DefaultTimingModel    );    PORT (        TC1             : IN    std_logic := 'U';        TC2             : IN    std_logic := 'U';        TC3             : IN    std_logic := 'U';        TC4             : IN    std_logic := 'U';        A               : IN    std_logic := 'U';        N1Y1            : OUT   std_logic := 'U';        N1Y2            : OUT   std_logic := 'U';        N2Y1            : OUT   std_logic := 'U';        N2Y2            : OUT   std_logic := 'U';        N3Y             : OUT   std_logic := 'U';        N4Y             : OUT   std_logic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of cdc328a : ENTITY IS TRUE;END cdc328a;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cdc328a IS    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;    SIGNAL TC1_ipd             : std_ulogic := 'X';    SIGNAL TC2_ipd             : std_ulogic := 'X';    SIGNAL TC3_ipd             : std_ulogic := 'X';    SIGNAL TC4_ipd             : std_ulogic := 'X';    SIGNAL A_ipd               : std_ulogic := 'X';BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1 : VitalWireDelay (TC1_ipd, TC1, tipd_TC1);        w_2 : VitalWireDelay (TC2_ipd, TC2, tipd_TC2);        w_3 : VitalWireDelay (TC3_ipd, TC3, tipd_TC3);        w_4 : VitalWireDelay (TC4_ipd, TC4, tipd_TC4);        w_5 : VitalWireDelay (A_ipd, A, tipd_A);    END BLOCK;    ----------------------------------------------------------------------------        -- VITALBehavior Process    ----------------------------------------------------------------------------        VITALBehavior1 : PROCESS(A_ipd, TC1_ipd)        -- Functionality Results Variables        VARIABLE Y_zd        : std_ulogic := 'X';        -- Output Glitch Detection Variables        VARIABLE Y0_GlitchData : VitalGlitchDataType;        VARIABLE Y1_GlitchData : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------                Y_zd := VitalXOR2(a=> A_ipd, b => TC1_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       =>  N1Y1,            OutSignalName   =>  "N1Y1",            OutTemp         =>  Y_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_N4Y,                      PathCondition     => TRUE ),                1 => (InputChangeTime   => TC1_ipd'LAST_EVENT,                      PathDelay         => tpd_TC4_N4Y,                      PathCondition     => TRUE ) ),            GlitchData      => Y0_GlitchData );        VitalPathDelay01 (            OutSignal       =>  N1Y2,            OutSignalName   =>  "N1Y2",            OutTemp         =>  Y_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_N4Y,                      PathCondition     => TRUE ),                1 => (InputChangeTime   => TC1_ipd'LAST_EVENT,                      PathDelay         => tpd_TC4_N4Y,                      PathCondition     => TRUE ) ),            GlitchData      => Y1_GlitchData );    END PROCESS VITALBehavior1;    ----------------------------------------------------------------------------        -- VITALBehavior Process    ----------------------------------------------------------------------------        VITALBehavior2 : PROCESS(A_ipd, TC2_ipd)        -- Functionality Results Variables        VARIABLE Y_zd        : std_ulogic := 'X';        -- Output Glitch Detection Variables        VARIABLE Y0_GlitchData : VitalGlitchDataType;        VARIABLE Y1_GlitchData : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------                Y_zd := VitalXOR2(a=> A_ipd, b => TC2_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       =>  N2Y1,            OutSignalName   =>  "N2Y1",            OutTemp         =>  Y_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_N4Y,                      PathCondition     => TRUE ),                1 => (InputChangeTime   => TC2_ipd'LAST_EVENT,                      PathDelay         => tpd_TC4_N4Y,                      PathCondition     => TRUE ) ),            GlitchData      => Y0_GlitchData );        VitalPathDelay01 (            OutSignal       =>  N2Y2,            OutSignalName   =>  "N2Y2",            OutTemp         =>  Y_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_N4Y,                      PathCondition     => TRUE ),                1 => (InputChangeTime   => TC2_ipd'LAST_EVENT,                      PathDelay         => tpd_TC4_N4Y,                      PathCondition     => TRUE ) ),            GlitchData      => Y1_GlitchData );    END PROCESS VITALBehavior2;    ----------------------------------------------------------------------------        -- VITALBehavior Process    ----------------------------------------------------------------------------        VITALBehavior3 : PROCESS(A_ipd, TC3_ipd)        -- Functionality Results Variables        VARIABLE Y_zd        : std_ulogic := 'X';        -- Output Glitch Detection Variables        VARIABLE Y_GlitchData : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------                Y_zd := VitalXOR2(a=> A_ipd, b => TC3_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       =>  N3Y,            OutSignalName   =>  "N3Y",            OutTemp         =>  Y_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_N4Y,                      PathCondition     => TRUE ),                1 => (InputChangeTime   => TC3_ipd'LAST_EVENT,                      PathDelay         => tpd_TC4_N4Y,                      PathCondition     => TRUE ) ),            GlitchData      => Y_GlitchData );    END PROCESS VITALBehavior3;    ----------------------------------------------------------------------------        -- VITALBehavior Process    ----------------------------------------------------------------------------        VITALBehavior4 : PROCESS(A_ipd, TC4_ipd)        -- Functionality Results Variables        VARIABLE Y_zd        : std_ulogic := 'X';        -- Output Glitch Detection Variables        VARIABLE Y_GlitchData : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------                Y_zd := VitalXOR2(a=> A_ipd, b => TC4_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       =>  N4Y,            OutSignalName   =>  "N4Y",            OutTemp         =>  Y_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_N4Y,                      PathCondition     => TRUE ),                1 => (InputChangeTime   => TC4_ipd'LAST_EVENT,                      PathDelay         => tpd_TC4_N4Y,                      PathCondition     => TRUE ) ),            GlitchData      => Y_GlitchData );    END PROCESS VITALBehavior4;END vhdl_behavioral;