----------------------------------------------------------------------------------  File Name: cdc341.vhd----------------------------------------------------------------------------------  Copyright (C) 1998-2002 Free Model Foundry; http://www.FreeModelFoundry.com/-- --  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.-- --  MODIFICATION HISTORY:-- --  version: |  author:  | mod date: | changes made:--    V1.0     R. Munden   98 MAY 11   Initial release--    V2.0     R. Munden   02 APR 12   flattened model----------------------------------------------------------------------------------  PART DESCRIPTION:-- --  Library:     CLOCK--  Technology:  TTL--  Part:        CDC341-- --  Description:  1-Line to 8-Line Clock Driver--------------------------------------------------------------------------------LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;                 USE IEEE.VITAL_timing.ALL;                 USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;     USE FMF.gen_utils.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cdc341 IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_G1             : VitalDelayType01 := VitalZeroDelay01;        tipd_G2             : VitalDelayType01 := VitalZeroDelay01;        tipd_A              : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays        tpd_A_Y1A           : VitalDelayType01 := UnitDelay01;        tpd_G1_Y1A          : VitalDelayType01 := UnitDelay01;        tpd_G2_Y2A          : VitalDelayType01 := UnitDelay01;        -- generic control parameters        MsgOn               : BOOLEAN := DefaultMsgOn;        XOn                 : Boolean  := DefaultXOn;        InstancePath        : STRING   := DefaultInstancePath;        -- For FMF SDF techonology file usage        TimingModel         : STRING   := DefaultTimingModel    );    PORT (        G1       : IN    std_ulogic := 'U';        G2       : IN    std_ulogic := 'U';        A        : IN    std_ulogic := 'U';        Y1A      : OUT   std_ulogic := 'U';        Y1B      : OUT   std_ulogic := 'U';        Y1C      : OUT   std_ulogic := 'U';        Y1D      : OUT   std_ulogic := 'U';        Y2A      : OUT   std_ulogic := 'U';        Y2B      : OUT   std_ulogic := 'U';        Y2C      : OUT   std_ulogic := 'U';        Y2D      : OUT   std_ulogic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of cdc341 : ENTITY IS TRUE;END cdc341;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cdc341 IS    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;    SIGNAL G1_ipd       : std_ulogic := 'U';    SIGNAL G2_ipd       : std_ulogic := 'U';    SIGNAL A_ipd        : std_ulogic := 'U';    SIGNAL Y1           : std_ulogic := 'U';    SIGNAL Y2           : std_ulogic := 'U';BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1: VitalWireDelay (G1_ipd, G1, tipd_G1);        w_2: VitalWireDelay (G2_ipd, G2, tipd_G2);        w_3: VitalWireDelay (A_ipd, A, tipd_A);    END BLOCK;    ----------------------------------------------------------------------------    -- Concurrent Procedures    ----------------------------------------------------------------------------    a_1: VitalIDENT (q => Y1A, a => Y1);    a_2: VitalIDENT (q => Y1B, a => Y1);    a_3: VitalIDENT (q => Y1C, a => Y1);    a_4: VitalIDENT (q => Y1D, a => Y1);    a_5: VitalIDENT (q => Y2A, a => Y2);    a_6: VitalIDENT (q => Y2B, a => Y2);    a_7: VitalIDENT (q => Y2C, a => Y2);    a_8: VitalIDENT (q => Y2D, a => Y2);    ----------------------------------------------------------------------------    -- Main Behavior Process    ----------------------------------------------------------------------------    VitalBehavior1 : PROCESS (A_ipd, G1_ipd)        -- Functionality Results Variables        VARIABLE Y1_zd           : std_ulogic;        -- Output Glitch Detection Variables        VARIABLE Y1_GlitchData   : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------        Y1_zd := VitalAND2 (a => A_ipd, b => G1_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       => Y1,            OutSignalName   => "Y1",            OutTemp         => Y1_zd,            GlitchData      => Y1_GlitchData,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_Y1A,                     PathCondition     => TRUE),                1 => (InputChangeTime   => G1_ipd'LAST_EVENT,                      PathDelay         => tpd_G1_Y1A,                      PathCondition     => TRUE))        );    END PROCESS;    VitalBehavior2 : PROCESS (A_ipd, G2_ipd)        -- Functionality Results Variables        VARIABLE Y2_zd           : std_ulogic;        -- Output Glitch Detection Variables        VARIABLE Y2_GlitchData   : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------        Y2_zd := VitalAND2 (a => A_ipd, b => G2_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       => Y2,            OutSignalName   => "Y2",            OutTemp         => Y2_zd,            GlitchData      => Y2_GlitchData,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => A_ipd'LAST_EVENT,                      PathDelay         => tpd_A_Y1A,                     PathCondition     => TRUE),                1 => (InputChangeTime   => G2_ipd'LAST_EVENT,                      PathDelay         => tpd_G2_Y2A,                      PathCondition     => TRUE))        );    END PROCESS;END vhdl_behavioral;