?? cdc536.ftm
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cdc536 Parts</TITLE><BODY><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 00 Jul 01 Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cdc536<FMFTIME>CDC536DB<SOURCE>Texas Instruments SCAS378F-Revised October 1998</SOURCE><COMMENT>CLK to Y path delay is zero because this is a PLL, OE to Y path delay is not specified by TI so I made one up</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLKIN Y1A (0:0:0) (0:0:0)) (IOPATH OENeg Y1A () () (2:2:2) (2:2:2) (2:2:2) (2:2:2)) )) (TIMINGCHECK (PERIOD (posedge FBIN) (20)) )</TIMING></FMFTIME></BODY></FTML>?? 快捷鍵說明
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