----------------------------------------------------------------------------------  File Name: cy2309nz.vhd----------------------------------------------------------------------------------  Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com/-- --  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.-- --  MODIFICATION HISTORY:-- --  version | author  | mod date | changes made--    V1.0  R. Munden  01 MAY 21  Initial release----------------------------------------------------------------------------------  PART DESCRIPTION:-- --  Library:     CLOCK--  Technology:  CMOS--  Part:        CY2309NZ-- --  Description:  Clock Driver--------------------------------------------------------------------------------LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;                 USE IEEE.VITAL_timing.ALL;                 USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;     USE FMF.gen_utils.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cy2309nz IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_I            : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays        tpd_I_O           : VitalDelayType01 := UnitDelay01;        -- generic control parameters        MsgOn             : BOOLEAN  := DefaultMsgOn;        XOn               : Boolean  := DefaultXOn;        InstancePath      : STRING   := DefaultInstancePath;        -- For FMF SDF techonology file usage        TimingModel       : STRING   := DefaultTimingModel    );    PORT (        I           : IN    std_ulogic := 'U';        O           : OUT   std_ulogic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of cy2309nz : ENTITY IS TRUE;END cy2309nz;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cy2309nz IS    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;    CONSTANT partID     : STRING := "CY2309NZ";    SIGNAL I_ipd        : std_ulogic := 'X';BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1: VitalWireDelay (I_ipd, I, tipd_I);    END BLOCK;    ----------------------------------------------------------------------------        -- VITALBehavior Process    ----------------------------------------------------------------------------        VITALBehavior : PROCESS(I_ipd)        -- Functionality Results Variables        VARIABLE O_zd        : std_ulogic := 'U';        -- Output Glitch Detection Variables        VARIABLE O_GlitchData : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------            O_zd := VitalBUF(data=> I_ipd);        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       =>  O,            OutSignalName   =>  "O",            OutTemp         =>  O_zd,            XOn             => XOn,            MsgOn           => MsgOn,            Paths           => (                0 => (InputChangeTime   => I_ipd'LAST_EVENT,                      PathDelay         => tpd_I_O,                      PathCondition     => TRUE ) ),            GlitchData      => O_GlitchData );    END PROCESS;END vhdl_behavioral;