----------------------------------------------------------------------------------  File name: roboclock.vhd----------------------------------------------------------------------------------  Copyright (C) 1997 Free Model Foundry http://www.FreeModelFoundry.com/----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.----  MODIFICATION HISTORY:-- --    version: |  author:  | mod date: | changes made:--      V2.0      L. Lee     96 SEP  3   Initial release--      V2.1     R. Munden   97 MAR 01   Changed XGenerationOn to XOn, added --                                       MsgOn, and updated TimingChecks & --                                       PathDelays--      V2.2     R. Steele   97 MAR 13   Removed configuration----------------------------------------------------------------------------------   PART DESCRIPTION :-- --   Library:       MISC--   Technology:    TTL     OR CMOS--   Part:          CY7B991 OR CY7B992-- --   Description:   Programmable Skew Clock Buffer-- --------------------------------------------------------------------------------LIBRARY IEEE;     USE IEEE.std_logic_1164.ALL;                  USE IEEE.std_logic_arith.ALL;                  USE IEEE.VITAL_timing.all;                  USE IEEE.VITAL_primitives.all;LIBRARY FMF;      USE FMF.gen_utils.all;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY roboclock IS    GENERIC (        -- note: this is a PLL device; so, no tpd generics        -- tipd delays: interconnect path delays        tipd_FB             : VitalDelayType01 := VitalZeroDelay01;        tipd_REF            : VitalDelayType01 := VitalZeroDelay01;        tipd_FS             : VitalDelayType01 := VitalZeroDelay01;        tipd_TEST           : VitalDelayType01 := VitalZeroDelay01;        -- tpw values: pulse widths        tpw_hi_min_REF      : VitalDelayType := UnitDelay;        tpw_lo_min_REF      : VitalDelayType := UnitDelay;        -- tperiod_min: minimum clock period = 1/max freq        tperiod_min_REF     : VitalDelayType := UnitDelay;        -- generic control parameters        InstancePath        : STRING  := DefaultInstancePath;        TimingChecksOn      : BOOLEAN := DefaultTimingChecks;        MsgOn               : BOOLEAN := DefaultMsgOn;        XOn                 : BOOLEAN := DefaultXOn;        -- For FMF SDF technology file usage        TimingModel         : STRING  := DefaultTimingModel    );    PORT (        -- 'Z' denotes internal MID state of peculiar three-state        -- input used by this part        REF             : IN  std_logic := 'U';        FB              : IN  std_logic := 'U';        FS              : IN  std_logic := 'Z';        TEST            : IN  std_logic := 'Z';        F10             : IN  std_logic := 'Z';        F11             : IN  std_logic := 'Z';        F20             : IN  std_logic := 'Z';        F21             : IN  std_logic := 'Z';        F30             : IN  std_logic := 'Z';        F31             : IN  std_logic := 'Z';        F40             : IN  std_logic := 'Z';        F41             : IN  std_logic := 'Z';        Q10             : OUT std_logic := 'U';        Q11             : OUT std_logic := 'U';        Q20             : OUT std_logic := 'U';        Q21             : OUT std_logic := 'U';        Q30             : OUT std_logic := 'U';        Q31             : OUT std_logic := 'U';        Q40             : OUT std_logic := 'U';        Q41             : OUT std_logic := 'U'    );    ATTRIBUTE VITAL_level0 OF roboclock : ENTITY IS TRUE;END roboclock;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral OF roboclock IS    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE;    SIGNAL      REF_ipd             : std_ulogic := 'X';    SIGNAL      FB_ipd              : std_ulogic := 'X';    SIGNAL      FS_ipd              : std_ulogic := 'Z';    SIGNAL      TEST_ipd            : std_ulogic := 'Z';    -- All lower case signals are internal to the model    SIGNAL      qa1                 : std_ulogic :='0';    SIGNAL      qa2                 : std_ulogic :='0';    SIGNAL      qa3                 : std_ulogic :='0';    SIGNAL      qa4                 : std_ulogic :='0';    SIGNAL      a                   : std_ulogic :='0';    SIGNAL      b                   : std_ulogic :='0';    SIGNAL      c                   : std_ulogic :='0';    SIGNAL      d                   : std_ulogic :='0';    SIGNAL      grid                    : std_ulogic := 'Z';    SIGNAL      f_nom                   : std_ulogic := '0';    SIGNAL      f_nom_period            : time:= 0 ns;    SIGNAL      f_nom_period_ini        : time:= 0 ns;    SIGNAL      f_nom_period_up_bond    : time:= 0 ns;    SIGNAL      f_nom_period_low_bond   : time:= 0 ns;    SIGNAL      f_nom_period_fin        : time:= 0 ns;    SIGNAL      tu                      : time:= 0 ns;    SIGNAL      ref_period              : time:= 0 ns;    SIGNAL      fb_period               : time:= 0 ns;    SIGNAL      grid_period             : time:= 0 ns;    SIGNAL      ref_count               : integer :=0;    SIGNAL      fb_count                : integer :=0;    SIGNAL      weight_count        : integer :=0;    SIGNAL      M                   : integer :=0;    SIGNAL      MP                  : integer :=0;    -- From Table 1. of the Cypress data sheet about this port    CONSTANT    N_low               : integer :=44;    CONSTANT    N_mid               : integer :=26;    CONSTANT    N_high              : integer :=16;BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1: VitalWireDelay (REF_ipd, REF, tipd_REF);        w_2: VitalWireDelay (FB_ipd, FB, tipd_FB);        w_3: VitalWireDelay (FS_ipd, FS, tipd_FS);        w_4: VitalWireDelay (TEST_ipd, TEST, tipd_TEST);    END BLOCK;----------------------------------------------------------------------------------  Nominal Frequency Process---------------------------------------------------------------------------------- This process generates nominal frequency (f_nom) signal.  M is the factor of-- reference frequency (REF_ipd) over nominal frequency.-- The period of nominal frequency (f_nom_period) is determined in -- Nominal Frequency Period Mux Process (f_nom_period_mux_process). -- Note that f_nom and REF_ipd are lined up by the wait statement.-- And the last "wait for (f_nom_period/2)" was void to prevent aliasing.-- During test mode (TEST_ipd='Z' or '1'), the PLL is disconnected-- from the output.  The device acts like a delay. Output simply is-- a delay signal of reference signal.--------------------------------------------------------------------------------    fnom_process:PROCESS    BEGIN        WAIT ON REF_ipd;        IF (TEST_ipd='0') THEN            IF (REF_ipd='1') THEN                IF (M=1) THEN                    f_nom <='1';                    wait for (f_nom_period/2);                    f_nom <= '0';                ELSIF (M=2 or M=4) THEN                       FOR i in 0 to M-2 LOOP                        f_nom <='1';                        wait for (f_nom_period/2);                        f_nom <= '0';                        wait for (f_nom_period/2);                    END LOOP;                        f_nom <='1';                        wait for (f_nom_period/2);                        f_nom <= '0';                ELSE                    NULL;                END IF;            END IF;        ELSIF (TEST_ipd='Z' or TEST_ipd='1') THEN            f_nom <= REF_ipd;        ELSE            NULL;        END IF;                 END PROCESS;----------------------------------------------------------------------------------  Search Mode & Operation Mode Mux Process---------------------------------------------------------------------------------- In this process, the output is muxed between the "feedback search" pins and -- the "real" output pins.  M=0 indicates "feedback search" mode, M=1,2,or 4-- indicates "operation" mode.-- mux1,mux2,mux3,mux4 represent the output of the mux. M is the select signal.-- When M is 0, output is connected to a,b,c,d to search feedback pin.-- When M is 1,2, or 4, output is connect to qa1,qa2,qa3,qa4 which are -- generated from f_nom.-- Note that 1Q0 and 1Q1 are identical (same as 2Q0 and 2Q1, 3Q0 and 3Q1, -- 4Q0 and 4Q1). Therefore, use mux1 to generate both 1Q0 and 1Q1.--------------------------------------------------------------------------------     mux_process:PROCESS(M,a,b,c,d,qa1,qa2,qa3,qa4,REF_ipd)        VARIABLE PD_REF         : VitalPeriodDataType := VitalPeriodDataInit;        VARIABLE Pviol_REF      : X01 := '0';    BEGIN        ------------------------------------------------------------------------        -- Timing Check Section        ------------------------------------------------------------------------        IF (TimingChecksOn) THEN            VitalPeriodPulseCheck (                TestSignal      =>  REF,                TestSignalName  =>  "REF",                Period          =>  tperiod_min_REF,                PulseWidthHigh  =>  tpw_hi_min_REF,                PulseWidthLow   =>  tpw_lo_min_REF,                PeriodData      =>  PD_REF,                XOn             =>  XOn,                MsgOn           =>  MsgOn,                Violation       =>  Pviol_REF,                HeaderMsg       =>  InstancePath & "RoboClock",                CheckEnabled    =>  TRUE );        END IF; -- Timing Check Section        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------        IF (Pviol_REF = 'X') THEN            Q10 <= 'X' ;            Q11 <= 'X' ;            Q20 <= 'X' ;            Q21 <= 'X' ;            Q30 <= 'X' ;            Q31 <= 'X' ;            Q40 <= 'X' ;            Q41 <= 'X' ;        ELSE            IF (M=0) THEN                 -- Search for the output pin connected to the feedback pin                Q10 <= a ;                Q11 <= a ;                Q20 <= b ;                Q21 <= b ;                Q30 <= c ;                Q31 <= c ;                Q40 <= d ;                Q41 <= d ;            ELSE                -- Operation mode output                Q10 <= qa1 ;                Q11 <= qa1 ;                Q20 <= qa2 ;                Q21 <= qa2 ;                Q30 <= qa3 ;                Q31 <= qa3 ;                Q40 <= qa4 ;                Q41 <= qa4 ;            END IF;         END IF;     END PROCESS;----------------------------------------------------------------------------------  Initialize Nominal Frequency Period & Time Unit DelayProcess---------------------------------------------------------------------------------- This process initializes nominal frequency period (f_nom_period_ini)-- and the time unit delay (tu)-- according to the input of the frequency state (FS_ipd) signal.-- The lower and upper bond of the frequency range were obtianed from-- Cypress databook.--------------------------------------------------------------------------------    f_nom_period_ini_process:PROCESS(FS_ipd,f_nom_period)        VARIABLE N       : integer:=0;    BEGIN        -- Initialized nominal frequency period by the select of input of FS pin        IF (FS_ipd='0') THEN            f_nom_period_ini<=44.44 ns;            f_nom_period_up_bond<=66.67 ns;            f_nom_period_low_bond<=33.33 ns;            N:=N_low;        ELSIF (FS_ipd='Z') THEN            f_nom_period_ini<=26.66 ns;            f_nom_period_up_bond<=40 ns;            f_nom_period_low_bond<=20 ns;            N:=N_mid;        ELSIF (FS_ipd='1') THEN            f_nom_period_ini<=16.66 ns;            f_nom_period_up_bond<=25 ns;