----------------------------------------------------------------------------------  File Name: m88915t.vhd----------------------------------------------------------------------------------  Copyright (C) 2000-2003 Free Model Foundry; http://www.FreeModelFoundry.com/-- --  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.-- --  MODIFICATION HISTORY:-- --  version: |  author:  | mod date: | changes made:--    V1.0    R. Munden    00 Sep 30   Initial release--    V1.1    R. Munden    02 Jan 29   modified use of _nwv to satisfy ncvhdl-- ----------------------------------------------------------------------------------  PART DESCRIPTION:-- --  Library:    CLOCK--  Technology: CMOS--  Part:       M88915T-- --  Description: PLL Clock Driver with 3-State Outputs--------------------------------------------------------------------------------LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;                USE IEEE.VITAL_timing.ALL;                USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;    USE FMF.gen_utils.ALL;                USE FMF.ff_package.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY m88915t IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_FBK                 : VitalDelayType01 := VitalZeroDelay01;        tipd_FREQSEL             : VitalDelayType01 := VitalZeroDelay01;        tipd_PLLEN               : VitalDelayType01 := VitalZeroDelay01;        tipd_REFSEL              : VitalDelayType01 := VitalZeroDelay01;        tipd_SYNC0               : VitalDelayType01 := VitalZeroDelay01;        tipd_SYNC1               : VitalDelayType01 := VitalZeroDelay01;        tipd_OE                  : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays        tpd_SYNC0_Q0             : VitalDelayType01 := UnitDelay01;        tpd_OE_Q0                : VitalDelayType01Z := UnitDelay01Z;        -- tperiod_min: minimum clock period = 1/max freq        tperiod_SYNC0_posedge    : VitalDelayType := UnitDelay;        -- generic control parameters        InstancePath        : STRING    := DefaultInstancePath;        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;        MsgOn               : BOOLEAN   := DefaultMsgOn;        XOn                 : BOOLEAN   := DefaultXon;        -- For FMF SDF technology file usage        TimingModel         : STRING    := DefaultTimingModel    );    PORT (        QX2             : OUT   std_ulogic := 'U';        FBK             : IN    std_ulogic := 'U';        FREQSEL         : IN    std_ulogic := 'U';        LOCK            : OUT   std_ulogic := 'U';        PLLEN           : IN    std_ulogic := 'U';        QDIV2           : OUT   std_ulogic := 'U';        Q0              : OUT   std_ulogic := 'U';        Q1              : OUT   std_ulogic := 'U';        Q2              : OUT   std_ulogic := 'U';        Q3              : OUT   std_ulogic := 'U';        Q4              : OUT   std_ulogic := 'U';        RC1             : IN    std_ulogic := 'U';        REFSEL          : IN    std_ulogic := 'U';        SYNC0           : IN    std_ulogic := 'U';        SYNC1           : IN    std_ulogic := 'U';        GNDAN           : OUT   std_ulogic := 'U';        VCCAN           : OUT   std_ulogic := 'U';        Q5Neg           : OUT   std_ulogic := 'U';        OE              : IN    std_ulogic := 'U'    );    ATTRIBUTE VITAL_LEVEL0 of m88915t : ENTITY IS TRUE;END m88915t;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of m88915t IS    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;    SIGNAL FBK_ipd             : std_ulogic := 'U';    SIGNAL FREQSEL_ipd         : std_ulogic := 'U';    SIGNAL PLLEN_ipd           : std_ulogic := 'U';    SIGNAL REFSEL_ipd          : std_ulogic := 'U';    SIGNAL SYNC0_ipd           : std_ulogic := 'U';    SIGNAL SYNC1_ipd           : std_ulogic := 'U';    SIGNAL SYNCin              : std_ulogic := 'U';    SIGNAL OE_ipd              : std_ulogic := 'U';    SIGNAL Q                   : std_ulogic := 'U';    SIGNAL FREQSEL_nwv         : UX01;    SIGNAL FBK_nwv             : UX01;    SIGNAL pll_out             : std_ulogic := '1';    SIGNAL mux_out             : std_ulogic := '1';    SIGNAL div_out             : std_ulogic := 'U';    SIGNAL rst_int             : std_ulogic := '1';    SIGNAL vco_lock            : boolean;    SIGNAL pll_delay           : time := 0 ns;    SIGNAL half_per            : time := 6 ns;    SIGNAL Violation           : X01 := '0';BEGIN    ----------------------------------------------------------------------------    -- Wire Delays    ----------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_2 : VitalWireDelay (FBK_ipd, FBK, tipd_FBK);        w_3 : VitalWireDelay (FREQSEL_ipd, FREQSEL, tipd_FREQSEL);        w_5 : VitalWireDelay (PLLEN_ipd, PLLEN, tipd_PLLEN);        w_13 : VitalWireDelay (REFSEL_ipd, REFSEL, tipd_REFSEL);        w_14 : VitalWireDelay (SYNC0_ipd, SYNC0, tipd_SYNC0);        w_15 : VitalWireDelay (SYNC1_ipd, SYNC1, tipd_SYNC1);        w_19 : VitalWireDelay (OE_ipd, OE, tipd_OE);    END BLOCK;    FREQSEL_nwv <= to_UX01(FREQSEL_ipd);    FBK_nwv <= to_UX01(FBK_ipd);    SYNCin <= VitalMux2(Data1 => SYNC1_ipd,                         Data0 => SYNC0_ipd,                        dSelect => REFSEL_ipd);    mux_out <= VitalMux2(Data1 => pll_out,                         Data0 => SYNC0_ipd,                        dSelect => PLLEN_ipd);    Q0 <= Q;    Q1 <= Q;    Q2 <= Q;    Q3 <= Q;    Q4 <= Q;    ----------------------------------------------------------------------------    -- ADJ Process    ----------------------------------------------------------------------------    ADJ : PROCESS (FBK_nwv, SYNCin)        VARIABLE vlck         : std_ulogic := '0';        VARIABLE fbk_period   : time := 0 ns;        VARIABLE sync_period  : time := 0 ns;        VARIABLE prev_sync    : time := 0 ns;        VARIABLE prev_fbk     : time := 0 ns;        VARIABLE toggle1      : boolean;        VARIABLE toggle2      : boolean;        -- Output Glitch Detection Variables        VARIABLE lock_GlitchData      : VitalGlitchDataType;    BEGIN        ------------------------------------------------------------------------        -- Functionality Section        ------------------------------------------------------------------------        IF rising_edge(SYNCin) THEN            sync_period := NOW - prev_sync;            prev_sync := NOW;            IF FBK_nwv = 'X' THEN               rst_int <= '1', '0' AFTER 5 ns;            END IF;        END IF;        IF (FBK_nwv'event AND FBK_nwv = '0') THEN            rst_int <= '0';            fbk_period := NOW - prev_fbk;            prev_fbk := NOW;            IF toggle1 AND not(toggle2) THEN                IF fbk_period > sync_period THEN                    half_per <= half_per - 50 ps;                    vco_lock <= false;                    vlck := '0';                ELSIF fbk_period < sync_period THEN                    half_per <= half_per + 60 ps;                    vco_lock <= false;                    vlck := '0';                ELSE                    vco_lock <= true;                    vlck := '1';                END IF;            END IF;            toggle1 := not toggle1;            IF toggle1 THEN                toggle2 := not toggle2;            ELSE                pll_delay <= 0 ps;            END IF;        END IF;        IF rising_edge(FBK_ipd) AND vco_lock AND toggle1 AND toggle2 THEN            IF (prev_sync + 350 ps) < NOW THEN                IF pll_delay < sync_period THEN                    pll_delay <= pll_delay - 60 ps;                END IF;            END IF;        END IF;        ------------------------------------------------------------------------        -- Path Delay Section        ------------------------------------------------------------------------        VitalPathDelay01 (            OutSignal       => LOCK,