?? cdc586.vhd
字號:
---------------------------------------------------------------------------------- File Name: cdc586.vhd---------------------------------------------------------------------------------- Copyright (C) 2000-2008 Free Model Foundry; http://www.FreeModelFoundry.com-- -- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.-- -- MODIFICATION HISTORY:-- -- version: | author: | mod date: | changes made:-- V1.0 R. Munden 00 Jul 06 Initial release-- V1.1 R. Munden 02 Mar 29 Corrected pulse check for ModelSim 5.6-- V1.2 R. Munden 08 Sep 25 Corrected signal name in ADJ-- ---------------------------------------------------------------------------------- PART DESCRIPTION:-- -- Library: CLOCK-- Technology: CMOS-- Part: CDC586-- -- Description: PLL Clock Driver with 3-State Outputs--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ff_package.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cdc586 IS GENERIC ( -- tipd delays: interconnect path delays tipd_FBIN : VitalDelayType01 := VitalZeroDelay01; tipd_CLKIN : VitalDelayType01 := VitalZeroDelay01; tipd_SEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_TEST : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLRNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLKIN_Y1A : VitalDelayType01 := UnitDelay01; tpd_OENeg_Y1A : VitalDelayType01Z := UnitDelay01Z; -- tperiod_min: minimum clock period = 1/max freq tperiod_FBIN_posedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( FBIN : IN std_ulogic := 'U'; CLKIN : IN std_ulogic := 'U'; SEL0 : IN std_ulogic := 'U'; SEL1 : IN std_ulogic := 'U'; TEST : IN std_ulogic := 'U'; Y1A : OUT std_ulogic := 'U'; Y1B : OUT std_ulogic := 'U'; Y1C : OUT std_ulogic := 'U'; Y2A : OUT std_ulogic := 'U'; Y2B : OUT std_ulogic := 'U'; Y2C : OUT std_ulogic := 'U'; Y3A : OUT std_ulogic := 'U'; Y3B : OUT std_ulogic := 'U'; Y3C : OUT std_ulogic := 'U'; Y4A : OUT std_ulogic := 'U'; Y4B : OUT std_ulogic := 'U'; Y4C : OUT std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; CLRNeg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cdc586 : ENTITY IS TRUE;END cdc586;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cdc586 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL FBIN_ipd : std_ulogic := 'U'; SIGNAL CLKIN_ipd : std_ulogic := 'U'; SIGNAL SEL0_ipd : std_ulogic := 'U'; SIGNAL SEL1_ipd : std_ulogic := 'U'; SIGNAL TEST_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL CLRNeg_ipd : std_ulogic := 'U'; SIGNAL pll_out : std_ulogic := '1'; SIGNAL tmux_out : std_ulogic := 'U'; SIGNAL omux1 : std_ulogic := '0'; SIGNAL omux2 : std_ulogic := '0'; SIGNAL omux3 : std_ulogic := '0'; SIGNAL nomux : std_ulogic := '0'; SIGNAL rst_int : std_ulogic := '0'; SIGNAL Y1 : std_ulogic := 'U'; SIGNAL Y2 : std_ulogic := 'U'; SIGNAL Y3 : std_ulogic := 'U'; SIGNAL Y4 : std_ulogic := 'U'; SIGNAL vco_lock : boolean; SIGNAL pll_delay : time := 0 ns; SIGNAL half_per : time := 6 ns; SIGNAL SEL : std_logic_vector(1 downto 0); SIGNAL CLKIN_nwv : UX01; SIGNAL OENeg_nwv : UX01; SIGNAL Violation : X01 := '0';BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (FBIN_ipd, FBIN, tipd_FBIN); w_2 : VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN); w_3 : VitalWireDelay (SEL0_ipd, SEL0, tipd_SEL0); w_4 : VitalWireDelay (SEL1_ipd, SEL1, tipd_SEL1); w_5 : VitalWireDelay (TEST_ipd, TEST, tipd_TEST); w_11 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_12 : VitalWireDelay (CLRNeg_ipd, CLRNeg, tipd_CLRNeg); END BLOCK; SEL <= (to_UX01(SEL1_ipd),to_UX01(SEL0_ipd)); CLKIN_nwv <= to_UX01(CLKIN_ipd); OENeg_nwv <= to_UX01(OENeg_ipd); Y1A <= Y1; Y1B <= Y1; Y1C <= Y1; Y2A <= Y2; Y2B <= Y2; Y2C <= Y2; Y3A <= Y3; Y3B <= Y3; Y3C <= Y3; Y4A <= Y4; Y4B <= Y4; Y4C <= Y4; ---------------------------------------------------------------------------- -- ADJ Process ---------------------------------------------------------------------------- ADJ : PROCESS (FBIN_ipd, CLKIN_ipd) VARIABLE fbi_period : time := 0 ns; VARIABLE clk_period : time := 0 ns; VARIABLE prev_clk : time := 0 ns; VARIABLE prev_fbi : time := 0 ns; VARIABLE toggle1 : boolean; VARIABLE toggle2 : boolean; -- Timing Check Variables VARIABLE Pviol_FBIN : X01 := '0'; VARIABLE PD_FBIN : VitalPeriodDataType := VitalPeriodDataInit; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => FBIN_ipd, TestSignalName => "FBIN", Period => tperiod_FBIN_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/cdc586", PeriodData => PD_FBIN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_FBIN ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation <= Pviol_FBIN; IF rising_edge(CLKIN_ipd) THEN clk_period := NOW - prev_clk; prev_clk := NOW; IF FBIN_ipd = 'X' THEN rst_int <= '1', '0' AFTER 5 ns; END IF; END IF; IF falling_edge(FBIN_ipd) THEN rst_int <= '0'; fbi_period := NOW - prev_fbi; prev_fbi := NOW; IF toggle1 AND toggle2 THEN IF fbi_period > clk_period THEN half_per <= half_per - 50 ps; vco_lock <= false; ELSIF fbi_period < clk_period THEN half_per <= half_per + 60 ps; vco_lock <= false; ELSE vco_lock <= true; END IF; END IF; toggle1 := not toggle1; IF toggle1 THEN toggle2 := not toggle2; ELSE pll_delay <= 0 ps; END IF; END IF; IF rising_edge(FBIN_ipd) AND vco_lock AND toggle1 AND toggle2 THEN IF (prev_clk + 350 ps) < NOW THEN IF pll_delay < clk_period THEN pll_delay <= pll_delay - 60 ps; END IF; END IF; END IF; END PROCESS ADJ; ---------------------------------------------------------------------------- -- PLL Process ---------------------------------------------------------------------------- PLL : PROCESS (pll_out) BEGIN pll_out <= TRANSPORT not pll_out AFTER pll_delay + half_per; END PROCESS PLL; ---------------------------------------------------------------------------- -- DIV2 Process ---------------------------------------------------------------------------- DIV2 : PROCESS (tmux_out, pll_out, CLKIN_nwv, TEST_ipd, SEL, CLRNeg_ipd, rst_int) -- Functionality Results Variables VARIABLE PrevData1 : std_logic_vector(0 to 2); VARIABLE CLK_div_2 : std_ulogic := '0'; BEGIN VitalStateTable ( StateTable => TFFR_tab, DataIn => (Violation, tmux_out, rst_int), Result => CLK_div_2, PreviousDataIn => PrevData1 ); IF TEST_ipd = '0' OR TEST_ipd = 'L' THEN tmux_out <= pll_out; ELSE tmux_out <= CLKIN_nwv; END IF; nomux <= tmux_out; CASE SEL IS WHEN "00" => omux1 <= tmux_out; omux2 <= tmux_out; omux3 <= tmux_out; WHEN "01" => omux1 <= CLK_div_2; omux2 <= tmux_out; omux3 <= tmux_out; WHEN "10" => omux1 <= CLK_div_2; omux2 <= CLK_div_2; omux3 <= tmux_out; WHEN "11" => omux1 <= CLK_div_2; omux2 <= CLK_div_2; omux3 <= CLK_div_2; WHEN others => -- error null; END CASE; END PROCESS DIV2; ---------------------------------------------------------------------------- -- OUTP Process ---------------------------------------------------------------------------- OUTP : PROCESS (OENeg_nwv, omux1, omux2, omux3, nomux) -- Functionality Results Variables VARIABLE Y1_zd : std_ulogic; VARIABLE Y2_zd : std_ulogic; VARIABLE Y3_zd : std_ulogic; VARIABLE Y4_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE Y1_GlitchData : VitalGlitchDataType; VARIABLE Y2_GlitchData : VitalGlitchDataType; VARIABLE Y3_GlitchData : VitalGlitchDataType; VARIABLE Y4_GlitchData : VitalGlitchDataType; BEGIN Y1_zd := VitalBUFIF0 (data => omux1, enable => OENeg_nwv); Y2_zd := VitalBUFIF0 (data => omux2, enable => OENeg_nwv); Y3_zd := VitalBUFIF0 (data => omux3, enable => OENeg_nwv); Y4_zd := VitalBUFIF0 (data => nomux, enable => OENeg_nwv); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => Y1, OutSignalName => "Y1", OutTemp => Y1_zd, GlitchData => Y1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => omux1'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLKIN_Y1A), PathCondition => TRUE), 1 => (InputChangeTime => OENeg_nwv'LAST_EVENT, PathDelay => tpd_OENeg_Y1A, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => Y2, OutSignalName => "Y2", OutTemp => Y2_zd, GlitchData => Y2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => omux2'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLKIN_Y1A), PathCondition => TRUE), 1 => (InputChangeTime => OENeg_nwv'LAST_EVENT, PathDelay => tpd_OENeg_Y1A, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => Y3, OutSignalName => "Y3", OutTemp => Y3_zd, GlitchData => Y3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => omux3'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLKIN_Y1A), PathCondition => TRUE), 1 => (InputChangeTime => OENeg_nwv'LAST_EVENT, PathDelay => tpd_OENeg_Y1A, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => Y4, OutSignalName => "Y4", OutTemp => Y4_zd, GlitchData => Y4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => nomux'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLKIN_Y1A), PathCondition => TRUE), 1 => (InputChangeTime => OENeg_nwv'LAST_EVENT, PathDelay => tpd_OENeg_Y1A, PathCondition => TRUE) ) ); END PROCESS OUTP;END vhdl_behavioral;?? 快捷鍵說明
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