----------------------------------------------------------------------------------  File Name: cy22395.vhd----------------------------------------------------------------------------------  Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com/----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.----  MODIFICATION HISTORY:----  version: |       author:     | mod date: | changes made:--    V1.0     V.Ljubisavljevic    05 Jan 14   Initial release----------------------------------------------------------------------------------  PART DESCRIPTION:----  Library:    CLOCK--  Technology: CMOS--  Part:       CY22395----  Description: Three-PLL Serial-Programmable Flash-Programmable Clock--               Generator----------------------------------------------------------------------------------LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;                USE IEEE.VITAL_timing.ALL;                USE IEEE.VITAL_primitives.ALL;LIBRARY FMF;    USE FMF.gen_utils.ALL;                USE FMF.conversions.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cy22395 IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_XTALIN             : VitalDelayType01  := VitalZeroDelay01;        tipd_SDAT               : VitalDelayType01Z := VitalZeroDelay01Z;        tipd_SCLK               : VitalDelayType01  := VitalZeroDelay01;        tipd_S2SUSPENDNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_SHUTDOWNNegOE      : VitalDelayType01  := VitalZeroDelay01;        --tsetup values        tsetup_SDAT_SCLK        : VitalDelayType:= UnitDelay;        --tpw values: pulse width        tpw_SCLK_posedge        : VitalDelayType := UnitDelay;        tpw_SCLK_negedge        : VitalDelayType := UnitDelay;        -- tperiod_min: minimum clock period = 1/max freq        tperiod_XTALIN          : VitalDelayType := UnitDelay;        tperiod_SCLK            : VitalDelayType := UnitDelay;        -- generic control parameters        InstancePath        : STRING    := DefaultInstancePath;        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;        MsgOn               : BOOLEAN   := DefaultMsgOn;        XOn                 : BOOLEAN   := DefaultXon;        -- For FMF SDF technology file usage        TimingModel         : STRING    := DefaultTimingModel        );    PORT (        XTALIN          : IN    std_logic := 'U';        SCLK            : IN    std_logic := 'U';        S2SUSPENDNeg    : IN    std_logic := 'U';        SHUTDOWNNegOE   : IN    std_logic := 'U';        SDAT            : INOUT std_logic := 'Z';        CLKA            : OUT   std_logic := 'U';        CLKB            : OUT   std_logic := 'U';        CLKC            : OUT   std_logic := 'U';        CLKD            : OUT   std_logic := 'U';        CLKE            : OUT   std_logic := 'U'        );    ATTRIBUTE VITAL_LEVEL0 of cy22395 : ENTITY IS TRUE;END cy22395;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cy22395 IS    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;    CONSTANT partID             : STRING := "cy22395";    CONSTANT DeviceAddress      : std_logic_vector(7 downto 0) := X"69";    CONSTANT MaxAddr            : NATURAL := 16#FF#;    SIGNAL XTALIN_ipd           : std_logic := 'U';    SIGNAL SDAT_ipd             : std_logic := 'U';    SIGNAL SCLK_ipd             : std_logic := 'U';    SIGNAL S2SUSPENDNeg_ipd     : std_logic := 'U';    SIGNAL SHUTDOWNNegOE_ipd    : std_logic := 'U';    SIGNAL PLL1_LOCK            : boolean;    SIGNAL PLL2_LOCK            : boolean;    SIGNAL PLL3_LOCK            : boolean;    SIGNAL MULT1_OUT            : std_logic := '0';    SIGNAL MULT2_OUT            : std_logic := '0';    SIGNAL MULT3_OUT            : std_logic := '0';    SIGNAL PLL1_OUT             : std_logic := '1';    SIGNAL PLL2_OUT             : std_logic := '1';    SIGNAL PLL3_OUT             : std_logic := '1';    SIGNAL DIV1_OUT             : std_logic := '1';    SIGNAL DIV2_OUT             : std_logic := '1';    SIGNAL DIV3_OUT             : std_logic := '1';    SIGNAL PostDivA_in          : std_logic;    SIGNAL PostDivB_in          : std_logic;    SIGNAL PostDivC_in          : std_logic;    SIGNAL PostDivD_in          : std_logic;    SIGNAL PostDivE_in          : std_logic;    SIGNAL PostDivA_out         : std_logic;    SIGNAL PostDivB_out         : std_logic;    SIGNAL PostDivC_out         : std_logic;    SIGNAL PostDivD_out         : std_logic;    SIGNAL PostDivE_out         : std_logic;    SIGNAL S2, S1, S0           : std_logic := '0';    ----------------------------------------------------------------------------    -- Registers    ----------------------------------------------------------------------------    SIGNAL R_08H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_09H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_0AH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_0BH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_0CH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_0DH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_0EH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_0FH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_10H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_11H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_12H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_13H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_14H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_15H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_16H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_17H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_40H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_41H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_42H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_43H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_44H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_45H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_46H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_47H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_48H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_49H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_4AH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_4BH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_4CH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_4DH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_4EH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_4FH : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_50H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_51H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_52H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_53H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_54H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_55H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_56H : std_logic_vector(7 downto 0) := "00000000";    SIGNAL R_57H : std_logic_vector(7 downto 0) := "00000000";    ALIAS ClkA0_FS0  : std_logic IS R_08H(7);    ALIAS ClkA1_FS0  : std_logic IS R_09H(7);    ALIAS ClkB0_FS0  : std_logic IS R_0AH(7);    ALIAS ClkB1_FS0  : std_logic IS R_0BH(7);    ALIAS ClkC_FS0   : std_logic IS R_0CH(7);    ALIAS ClkD_FS0   : std_logic IS R_0DH(7);    ALIAS ClkA0_Div  : std_logic_vector(6 downto 0) IS R_08H(6 downto 0);    ALIAS ClkA1_Div  : std_logic_vector(6 downto 0) IS R_09H(6 downto 0);    ALIAS ClkB0_Div  : std_logic_vector(6 downto 0) IS R_0AH(6 downto 0);    ALIAS ClkB1_Div  : std_logic_vector(6 downto 0) IS R_0BH(6 downto 0);    ALIAS ClkC_Div   : std_logic_vector(6 downto 0) IS R_0CH(6 downto 0);    ALIAS ClkD_Div   : std_logic_vector(6 downto 0) IS R_0DH(6 downto 0);    ALIAS ClkA_FS21  : std_logic_vector(1 downto 0) IS R_0EH(1 downto 0);    ALIAS ClkB_FS21  : std_logic_vector(1 downto 0) IS R_0EH(3 downto 2);    ALIAS ClkC_FS21  : std_logic_vector(1 downto 0) IS R_0EH(5 downto 4);    ALIAS ClkD_FS21  : std_logic_vector(1 downto 0) IS R_0EH(7 downto 6);    ALIAS ClkE_Div   : std_logic_vector(1 downto 0) IS R_0FH(1 downto 0);    ALIAS PdnEn      : std_logic IS R_0FH(3);    ALIAS PLL2_Q     : std_logic_vector(7 downto 0) IS R_11H;    ALIAS PLL2_P98   : std_logic_vector(1 downto 0) IS R_13H(1 downto 0);    ALIAS PLL2_P70   : std_logic_vector(7 downto 0) IS R_12H;    ALIAS PLL2_P0    : std_logic IS R_13H(2);    ALIAS PLL2_En    : std_logic IS R_13H(6);    ALIAS PLL3_Q     : std_logic_vector(7 downto 0) IS R_14H;    ALIAS PLL3_P98   : std_logic_vector(1 downto 0) IS R_16H(1 downto 0);    ALIAS PLL3_P70   : std_logic_vector(7 downto 0) IS R_15H;    ALIAS PLL3_P0    : std_logic IS R_16H(2);    ALIAS PLL3_En    : std_logic IS R_16H(6);    SIGNAL Pll1A_Q      : std_logic_vector(7 DOWNTO 0) := "00000000";    SIGNAL PLL1A_P98    : std_logic_vector(1 downto 0) := "00";    SIGNAL PLL1A_P70    : std_logic_vector(7 downto 0) := "00000000";    SIGNAL PLL1A_P0     : std_logic                    := '0';    SIGNAL PLL1A_En     : std_logic                    := '0';    SIGNAL PLL1A_DivSel : std_logic                    := '0';    SIGNAL Pll1B_Q      : std_logic_vector(7 DOWNTO 0) := "00000000";    SIGNAL PLL1B_P98    : std_logic_vector(1 downto 0) := "00";    SIGNAL PLL1B_P70    : std_logic_vector(7 downto 0) := "00000000";    SIGNAL PLL1B_P0     : std_logic                    := '0';    SIGNAL PLL1B_En     : std_logic                    := '0';    SIGNAL PLL1B_DivSel : std_logic                    := '0';    SIGNAL PLL1_Q       : std_logic_vector(7 downto 0) := "00000000";    SIGNAL PLL1_P98     : std_logic_vector(1 downto 0) := "00";    SIGNAL PLL1_P70     : std_logic_vector(7 downto 0) := "00000000";    SIGNAL PLL1_P0      : std_logic                    := '0';    SIGNAL PLL1_En      : std_logic                    := '0';    SIGNAL PLL1_DivSel  : std_logic                    := '0';    FUNCTION NOTz(s : std_logic) RETURN std_logic IS    BEGIN        IF (s = 'Z') THEN            RETURN 'Z';        ELSE            RETURN NOT s;        END IF;    END NOTz;    FUNCTION NOT1(s : std_logic) RETURN std_logic IS    BEGIN        IF (s = 'Z') THEN            RETURN '1';        ELSE            RETURN NOT s;        END IF;    END NOT1;BEGIN    ---------------------------------------------------------------------------    -- Wire Delays    ---------------------------------------------------------------------------    WireDelay : BLOCK    BEGIN        w_1   : VitalWireDelay(            XTALIN_ipd, XTALIN, tipd_XTALIN );        w_2   : VitalWireDelay(            SDAT_ipd, SDAT, tipd_SDAT );        w_3   : VitalWireDelay(            SCLK_ipd, SCLK, tipd_SCLK );        w_4   : VitalWireDelay(            S2SUSPENDNeg_ipd, S2SUSPENDNeg, tipd_S2SUSPENDNeg );        w_5   : VitalWireDelay(            SHUTDOWNNegOE_ipd, SHUTDOWNNegOE, tipd_SHUTDOWNNegOE );    END BLOCK;    ---------------------------------------------------------------------------    -- Main Behavior Block    ---------------------------------------------------------------------------    Behavior: BLOCK    BEGIN        S2 <= S2SUSPENDNeg;        -- purpose: Latching of S0 on power up        -- type   : combinational        -- outputs: S0        S0_Latching: PROCESS            VARIABLE first  : BOOLEAN := true;        BEGIN  -- PROCESS S0_Latching            IF first THEN                first := false;                S0 <= SDAT;            ELSE                WAIT;            END IF;        END PROCESS S0_Latching;        -- purpose: Latching of SCLK pin in S1 signal on startup        -- type   : combinational        -- inputs :        -- outputs: S1        S1_Latching: PROCESS            VARIABLE first  : BOOLEAN := true;        BEGIN  -- PROCESS S1_Latching            IF first THEN                S1 <= SCLK;                first := false;            ELSE                WAIT;            END IF;        END PROCESS S1_Latching;        -----------------------------------------------------------------------        -- Selector Process        -----------------------------------------------------------------------        Selector01 : PROCESS(S1, S0,R_40H,R_41H,R_42H,R_43H,R_44H,R_45H,R_46H,                             R_47H,R_48H,R_49H,R_4AH,R_4BH,R_4CH,R_4DH,R_4EH,                             R_4FH,R_50H,R_51H,R_52H,                             R_53H,R_54H,R_55H,R_56H,R_57H)            VARIABLE S : natural range 0 to 3;        BEGIN            S := to_nat((S1,S0));            CASE S IS                WHEN 0 =>                    PLL1A_Q      <= R_40H;                    PLL1A_P98    <= R_42H(1 downto 0);                    PLL1A_P70    <= R_41H;                    PLL1A_P0     <= R_42H(2);                    PLL1A_En     <= R_42H(6);                    PLL1A_DivSel <= R_42H(7);                    PLL1B_Q      <= R_4CH;                    PLL1B_P98    <= R_4EH(1 downto 0);                    PLL1B_P70    <= R_4DH;                    PLL1B_P0     <= R_4EH(2);                    PLL1B_En     <= R_4EH(6);                    PLL1B_DivSel <= R_4EH(7);                WHEN 1 =>                    PLL1A_Q      <= R_43H;                    PLL1A_P98    <= R_45H(1 downto 0);                    PLL1A_P70    <= R_44H;                    PLL1A_P0     <= R_45H(2);                    PLL1A_En     <= R_45H(6);                    PLL1A_DivSel <= R_45H(7);                    PLL1B_Q      <= R_4FH;                    PLL1B_P98    <= R_51H(1 downto 0);                    PLL1B_P70    <= R_50H;                    PLL1B_P0     <= R_51H(2);                    PLL1B_En     <= R_51H(6);                    PLL1B_DivSel <= R_51H(7);                WHEN 2 =>                    PLL1A_Q      <= R_46H;