?? cy22395.vhd
字號:
WHEN 2 => div_in := 2; WHEN 3 => div_in := 3; WHEN OTHERS => NULL; END CASE; IF div_in > 0 AND PostDivE_in /= 'Z' THEN IF PostDivE_in'event THEN IF first THEN PostDivE_out <= PostDivE_in; first := false; div_cnt := div_cnt + 1; ELSIF div_cnt < div_in THEN div_cnt := div_cnt + 1; ELSE div_cnt := 1; PostDivE_out <= NOT1(PostDivE_out); END IF; END IF; ELSE first := true; div_cnt := 0; PostDivE_out <= 'Z'; END IF; END PROCESS POST_DIV_E; CLKA <= PostDivA_out WHEN SHUTDOWNNegOE_ipd = '1' ELSE 'Z'; CLKB <= PostDivB_out WHEN SHUTDOWNNegOE_ipd = '1' ELSE 'Z'; CLKC <= PostDivC_out WHEN SHUTDOWNNegOE_ipd = '1' ELSE 'Z'; CLKD <= PostDivD_out WHEN SHUTDOWNNegOE_ipd = '1' ELSE 'Z'; CLKE <= PostDivE_out WHEN SHUTDOWNNegOE_ipd = '1' ELSE 'Z'; ----------------------------------------------------------------------- -- Serial Interface ----------------------------------------------------------------------- Serial : PROCESS (SDAT_ipd, SCLK_ipd) -- Type definitions TYPE SPI_State IS (STOP, START, IGNORE, READ, ADDRESS, WRITE ); VARIABLE State : SPI_State; VARIABLE BitCount : natural range 7 DOWNTO 0; VARIABLE RegAddr : natural range 0 to MaxAddr := 0; VARIABLE TmpByte : std_logic_vector(7 downto 0); VARIABLE SDAT_nwv : X01; VARIABLE SCLK_nwv : X01; VARIABLE Ack : boolean := false; VARIABLE WaitAck : boolean := false; -- Timing Check Variables VARIABLE Tviol_SDAT_SCLK : X01 := '0'; VARIABLE TD_SDAT_SCLK : VitalTimingDataType; VARIABLE Pviol_SCLK : X01 := '0'; VARIABLE PD_SCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE SDAT_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SDAT_GlitchData : VitalGlitchDataType; PROCEDURE Write( addr: natural; value: std_logic_vector(7 downto 0)) IS BEGIN CASE addr IS WHEN 16#08# => R_08H <= value; WHEN 16#09# => R_09H <= value; WHEN 16#0A# => R_0AH <= value; WHEN 16#0B# => R_0BH <= value; WHEN 16#0C# => R_0CH <= value; WHEN 16#0D# => R_0DH <= value; WHEN 16#0E# => R_0EH <= value; WHEN 16#0F# => R_0FH <= value; WHEN 16#10# => R_10H <= value; WHEN 16#11# => R_11H <= value; WHEN 16#12# => R_12H <= value; WHEN 16#13# => R_13H <= value; WHEN 16#14# => R_14H <= value; WHEN 16#15# => R_15H <= value; WHEN 16#16# => R_16H <= value; WHEN 16#17# => R_17H <= value; WHEN 16#40# => R_40H <= value; WHEN 16#41# => R_41H <= value; WHEN 16#42# => R_42H <= value; WHEN 16#43# => R_43H <= value; WHEN 16#44# => R_44H <= value; WHEN 16#45# => R_45H <= value; WHEN 16#46# => R_46H <= value; WHEN 16#47# => R_47H <= value; WHEN 16#48# => R_48H <= value; WHEN 16#49# => R_49H <= value; WHEN 16#4A# => R_4AH <= value; WHEN 16#4B# => R_4BH <= value; WHEN 16#4C# => R_4CH <= value; WHEN 16#4D# => R_4DH <= value; WHEN 16#4E# => R_4EH <= value; WHEN 16#4F# => R_4FH <= value; WHEN 16#50# => R_50H <= value; WHEN 16#51# => R_51H <= value; WHEN 16#52# => R_52H <= value; WHEN 16#53# => R_53H <= value; WHEN 16#54# => R_54H <= value; WHEN 16#55# => R_55H <= value; WHEN 16#56# => R_56H <= value; WHEN 16#57# => R_57H <= value; WHEN OTHERS => NULL; END CASE; END Write; IMPURE FUNCTION Read(addr: natural) RETURN natural IS VARIABLE value : natural; BEGIN CASE addr IS WHEN 16#08# => value := to_nat(R_08H); WHEN 16#09# => value := to_nat(R_09H); WHEN 16#0A# => value := to_nat(R_0AH); WHEN 16#0B# => value := to_nat(R_0BH); WHEN 16#0C# => value := to_nat(R_0CH); WHEN 16#0D# => value := to_nat(R_0DH); WHEN 16#0E# => value := to_nat(R_0EH); WHEN 16#0F# => value := to_nat(R_0FH); WHEN 16#10# => value := to_nat(R_10H); WHEN 16#11# => value := to_nat(R_11H); WHEN 16#12# => value := to_nat(R_12H); WHEN 16#13# => value := to_nat(R_13H); WHEN 16#14# => value := to_nat(R_14H); WHEN 16#15# => value := to_nat(R_15H); WHEN 16#16# => value := to_nat(R_16H); WHEN 16#17# => value := to_nat(R_17H); WHEN 16#40# => value := to_nat(R_40H); WHEN 16#41# => value := to_nat(R_41H); WHEN 16#42# => value := to_nat(R_42H); WHEN 16#43# => value := to_nat(R_43H); WHEN 16#44# => value := to_nat(R_44H); WHEN 16#45# => value := to_nat(R_45H); WHEN 16#46# => value := to_nat(R_46H); WHEN 16#47# => value := to_nat(R_47H); WHEN 16#48# => value := to_nat(R_48H); WHEN 16#49# => value := to_nat(R_49H); WHEN 16#4A# => value := to_nat(R_4AH); WHEN 16#4B# => value := to_nat(R_4BH); WHEN 16#4C# => value := to_nat(R_4CH); WHEN 16#4D# => value := to_nat(R_4DH); WHEN 16#4E# => value := to_nat(R_4EH); WHEN 16#4F# => value := to_nat(R_4FH); WHEN 16#50# => value := to_nat(R_50H); WHEN 16#51# => value := to_nat(R_51H); WHEN 16#52# => value := to_nat(R_52H); WHEN 16#53# => value := to_nat(R_53H); WHEN 16#54# => value := to_nat(R_54H); WHEN 16#55# => value := to_nat(R_55H); WHEN 16#56# => value := to_nat(R_56H); WHEN 16#57# => value := to_nat(R_57H); WHEN OTHERS => value := 0; END CASE; RETURN value; END Read; BEGIN SDAT_nwv := to_X01(SDAT_ipd); SCLK_nwv := to_X01(SCLK); ------------------------------------------------------------------- -- Timing Check Section ------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => SDAT_ipd, TestSignalName => "SDAT", RefSignal => SCLK_ipd, RefSignalName => "SCLK", SetupHigh => tsetup_SDAT_SCLK, SetupLow => tsetup_SDAT_SCLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/cy22395", TimingData => TD_SDAT_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAT_SCLK ); VitalPeriodPulseCheck ( TestSignal => SCLK_ipd, TestSignalName => "SCLK", Period => tperiod_SCLK, PulseWidthHigh => tpw_SCLK_posedge, PulseWidthLow => tpw_SCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/cy22395", PeriodData => PD_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLK ); END IF; ------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------ Violation := Tviol_SDAT_SCLK OR Pviol_SCLK; ASSERT Violation = '0' REPORT InstancePath & " control registers may be" & " incorret due to I2C timing violation(s)" SEVERITY Warning; IF (falling_edge(SDAT_ipd) AND SCLK_ipd'stable AND SCLK_nwv = '1') THEN State := START; BitCount := 0; ELSIF (rising_edge(SDAT_ipd) AND SCLK_ipd'stable AND SCLK_nwv = '1') THEN State := STOP; END IF; IF (rising_edge(SCLK_ipd) AND Ack = false) THEN CASE State IS WHEN START => TmpByte(7-BitCount) := SDAT_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSIF (TmpByte(7 DOWNTO 1) = DeviceAddress(6 downto 0)) THEN IF TmpByte(0) = '0' THEN State := ADDRESS; ELSE State := READ; WaitAck := true; TmpByte := to_slv(Read(RegAddr),8); END IF; Ack := true; ELSE State := IGNORE; END IF; WHEN ADDRESS => TmpByte(7 - BitCount) := SDAT_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSE RegAddr := to_nat(TmpByte); State := WRITE; Ack := true; END IF; WHEN WRITE => TmpByte(7 - BitCount) := SDAT_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSE Write(RegAddr, TmpByte); RegAddr := (RegAddr + 1) MOD (MaxAddr + 1); Ack := true; END IF; WHEN OTHERS => NULL; END CASE; ELSIF falling_edge(SCLK_ipd) THEN CASE State IS WHEN READ => IF (BitCount < 7) THEN SDAT_zd := TmpByte(7 - BitCount); BitCount := BitCount + 1; ELSIF WaitAck = false THEN SDAT_zd := TmpByte(7 - BitCount); RegAddr := (RegAddr + 1) MOD (MaxAddr + 1); WaitAck := true; ELSE IF (Ack = true) THEN SDAT_zd := '0'; Ack := false; ELSE SDAT_zd := 'Z'; END IF; BitCount := 0; WaitAck := false; TmpByte := to_slv(Read(RegAddr),8); END IF; WHEN OTHERS => NULL; END CASE; END IF; IF (falling_edge(SCLK_ipd) AND Ack = true AND State /= READ) THEN IF (SDAT_zd = '0') THEN Ack := false; SDAT_zd := 'Z'; BitCount := 0; ELSE SDAT_zd := '0'; END IF; END IF; ------------------------------------------------------------------- -- Path Delay Section ------------------------------------------------------------------- VitalPathDelay01Z ( OutSignal => SDAT, OutSignalName => "SDAT", OutTemp => SDAT_zd, Paths => ( 0 => (InputChangeTime => SCLK_ipd'LAST_EVENT, PathDelay => UnitDelay01Z, PathCondition => TRUE ) ), GlitchData => SDAT_GlitchData ); END PROCESS Serial; END BLOCK;END vhdl_behavioral;?? 快捷鍵說明
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