?? ring.rpt
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# !secldis1 & !secldis2;
-- Node name is '~391~2'
-- Equation name is '~391~2', location is LC8_C9, type is buried.
-- synthesized logic cell
_LC8_C9 = LCELL( _EQ002);
_EQ002 = _LC1_C9 & !_LC2_C9 & !sechdis1 & sechdis2;
-- Node name is '~391~3'
-- Equation name is '~391~3', location is LC4_C11, type is buried.
-- synthesized logic cell
_LC4_C11 = LCELL( _EQ003);
_EQ003 = _LC8_C9 & minhdis0 & minhdis2 & sechdis0;
-- Node name is ':391'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = LCELL( _EQ004);
_EQ004 = _LC4_C11 & minldis0 & minldis3;
-- Node name is '~426~1'
-- Equation name is '~426~1', location is LC1_C9, type is buried.
-- synthesized logic cell
_LC1_C9 = LCELL( _EQ005);
_EQ005 = !minhdis1 & !minldis1 & !minldis2 & !secldis0;
-- Node name is '~426~2'
-- Equation name is '~426~2', location is LC6_C9, type is buried.
-- synthesized logic cell
_LC6_C9 = LCELL( _EQ006);
_EQ006 = _LC1_C9 & !sechdis1 & !secldis1 & !secldis2;
-- Node name is '~426~3'
-- Equation name is '~426~3', location is LC2_C11, type is buried.
-- synthesized logic cell
_LC2_C11 = LCELL( _EQ007);
_EQ007 = _LC6_C9 & !minhdis2 & !sechdis0 & !sechdis2;
-- Node name is '~426~4'
-- Equation name is '~426~4', location is LC3_C11, type is buried.
-- synthesized logic cell
_LC3_C11 = LCELL( _EQ008);
_EQ008 = _LC2_C11 & !minhdis0 & !minldis0 & !minldis3;
-- Node name is '~474~1'
-- Equation name is '~474~1', location is LC4_C9, type is buried.
-- synthesized logic cell
_LC4_C9 = LCELL( _EQ009);
_EQ009 = alarm_minldis1 & alarm_minldis2 & minldis1 & minldis2
# alarm_minldis1 & !alarm_minldis2 & minldis1 & !minldis2
# !alarm_minldis1 & alarm_minldis2 & !minldis1 & minldis2
# !alarm_minldis1 & !alarm_minldis2 & !minldis1 & !minldis2;
-- Node name is '~474~2'
-- Equation name is '~474~2', location is LC1_C8, type is buried.
-- synthesized logic cell
_LC1_C8 = LCELL( _EQ010);
_EQ010 = alarm_hourldis0 & alarm_minldis0 & hourldis0 & minldis0
# alarm_hourldis0 & !alarm_minldis0 & hourldis0 & !minldis0
# !alarm_hourldis0 & alarm_minldis0 & !hourldis0 & minldis0
# !alarm_hourldis0 & !alarm_minldis0 & !hourldis0 & !minldis0;
-- Node name is '~474~3'
-- Equation name is '~474~3', location is LC3_C8, type is buried.
-- synthesized logic cell
_LC3_C8 = LCELL( _EQ011);
_EQ011 = alarm_minhdis1 & alarm_minhdis2 & minhdis1 & minhdis2
# alarm_minhdis1 & !alarm_minhdis2 & minhdis1 & !minhdis2
# !alarm_minhdis1 & alarm_minhdis2 & !minhdis1 & minhdis2
# !alarm_minhdis1 & !alarm_minhdis2 & !minhdis1 & !minhdis2;
-- Node name is '~474~4'
-- Equation name is '~474~4', location is LC4_C8, type is buried.
-- synthesized logic cell
_LC4_C8 = LCELL( _EQ012);
_EQ012 = alarm_minhdis0 & alarm_minldis3 & minhdis0 & minldis3
# !alarm_minhdis0 & alarm_minldis3 & !minhdis0 & minldis3
# alarm_minhdis0 & !alarm_minldis3 & minhdis0 & !minldis3
# !alarm_minhdis0 & !alarm_minldis3 & !minhdis0 & !minldis3;
-- Node name is '~474~5'
-- Equation name is '~474~5', location is LC5_C8, type is buried.
-- synthesized logic cell
_LC5_C8 = LCELL( _EQ013);
_EQ013 = _LC1_C8 & _LC3_C8 & _LC4_C8 & _LC4_C9;
-- Node name is '~474~6'
-- Equation name is '~474~6', location is LC1_A10, type is buried.
-- synthesized logic cell
_LC1_A10 = LCELL( _EQ014);
_EQ014 = alarm_hourhdis0 & alarm_hourldis3 & hourhdis0 & hourldis3
# !alarm_hourhdis0 & alarm_hourldis3 & !hourhdis0 & hourldis3
# alarm_hourhdis0 & !alarm_hourldis3 & hourhdis0 & !hourldis3
# !alarm_hourhdis0 & !alarm_hourldis3 & !hourhdis0 & !hourldis3;
-- Node name is '~474~7'
-- Equation name is '~474~7', location is LC2_A10, type is buried.
-- synthesized logic cell
_LC2_A10 = LCELL( _EQ015);
_EQ015 = alarm_hourhdis1 & hourhdis1 & _LC1_A10
# !alarm_hourhdis1 & !hourhdis1 & _LC1_A10;
-- Node name is '~474~8'
-- Equation name is '~474~8', location is LC6_C8, type is buried.
-- synthesized logic cell
_LC6_C8 = LCELL( _EQ016);
_EQ016 = alarm_hourldis1 & alarm_hourldis2 & hourldis1 & hourldis2
# alarm_hourldis1 & !alarm_hourldis2 & hourldis1 & !hourldis2
# !alarm_hourldis1 & alarm_hourldis2 & !hourldis1 & hourldis2
# !alarm_hourldis1 & !alarm_hourldis2 & !hourldis1 & !hourldis2;
-- Node name is ':474'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ017);
_EQ017 = alarm_switch & _LC2_A10 & _LC5_C8 & _LC6_C8;
-- Node name is '~505~1'
-- Equation name is '~505~1', location is LC6_C11, type is buried.
-- synthesized logic cell
_LC6_C11 = LCELL( _EQ018);
_EQ018 = freq_h & !_LC5_C11;
-- Node name is ':505'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = LCELL( _EQ019);
_EQ019 = _LC3_C11 & _LC6_C11 & !secldis3
# _LC2_C8 & _LC6_C11;
-- Node name is ':511'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ020);
_EQ020 = _LC7_C11 & !RESET
# freq_l & _LC5_C11 & !RESET;
Project Information d:\progra~1\maxplus2\maxplusworks\clock1\ring.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,048K
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