?? display.rpt
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Project Information d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/25/2008 17:08:03
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DISPLAY
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
display EP1K30QC208-3 40 11 0 0 0 % 202 11 %
User Pins: 40 11 0
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
***** Logic for device 'display' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
a a
a a l l
l l a a
a a r r
r r m m
m m _ _
_ _ h h h h
m m R R R m R R R R R R R o o R R o m m o R R s R R R R R R R R R R R R R m R R R R
i i E E E i E S E S E E E E E u u E E u i i u E E e E E E E E E E E E E E E E i E E E E
n n S S S n S V E S E S S S S S r r S S r V n n r S S c S S S S S S S S S S S S S n S S S S
l h E E E h E C C E C E E E V E E l l E E l C l l h E E V h E E E E E E E E E E V E E E l E E E E
d d R R R d R C D R D R R R C R R d d R R d C d d d R R C d R R R R R R R R R R C R R R d R R R R
i i V V V i V I I V I V V V C V V i i V G V i I i i i G V V C i V V V V V G V V V V V C V V V i V V V V
s s E E E s E N S E S E E E I E E s s E N E s N s s s N E E I s E E E E E N E E E E E I E E E s E E E E
2 1 D D D 1 D T 1 D 5 D D D O D D 2 1 D D D 3 T 3 0 1 D D D O 1 D D D D D D D D D D D O D D D 2 D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
ADDSEL0 | 16 141 | RESERVED
SECDIS6 | 17 140 | RESERVED
SECDIS0 | 18 139 | RESERVED
ADDSEL1 | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | minhdis0
VCCIO | 22 135 | alarm_minldis3
GND | 23 134 | hourldis3
hourldis1 | 24 133 | alarm_hourhdis1
RESET | 25 132 | hourldis0
RESERVED | 26 131 | alarm_minhdis2
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
ADDSEL2 | 28 129 | GND
RESERVED | 29 128 | SECDIS7
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | weekdis3
VCCIO | 42 115 | weekdis1
GND | 43 114 | secldis2
sechdis2 | 44 113 | secldis1
secldis0 | 45 112 | sechdis0
weekdis2 | 46 111 | minldis1
weekdis0 | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R S R R R a G R a a R a a V S R a R S V m R R G V m S h G G R V R R R R R R V R R R R R R V R R R R s R
E E E E E l N E l l E l l C E E l E E C i E E N C o C o N N E C E E E E E E C E E E E E E C E E E E e E
S C S S S a D S a a S a a C C S a S C C n S S D C d L u D D S C S S S S S S C S S S S S S C S S S S c S
E D E E E r E r r E r r I D E r E D I h E E I e K r E I E E E E E E I E E E E E E I E E E E l E
R I R R R m R m m R m m O I R m R I N d R R N h R O R R R R R R N R R R R R R O R R R R d R
V S V V V _ V _ _ V _ _ S V _ V S T i V V T d V V V V V V V T V V V V V V V V V V i V
E 2 E E E h E m h E h m 4 E m E 3 s E E i E E E E E E E E E E E E E E E E E s E
D D D D o D i o D o i D i D 2 D D s D D D D D D D D D D D D D D D D D 3 D
u n u u n n 0
r l r r l h
h d l l d d
d i d d i i
i s i i s s
s 1 s s 0 0
0 2 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C19 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C20 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
C22 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
C23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
C25 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
C26 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
C27 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
C28 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
C29 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
C30 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C31 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
C32 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
C33 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
C34 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C35 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
C36 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
D20 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
D33 8/ 8(100%) 7/ 8( 87%) 7/ 8( 87%) 1/2 0/2 5/22( 22%)
D34 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
F6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 3/22( 13%)
F7 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 14/22( 63%)
F10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F11 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 18/22( 81%)
F12 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
F13 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
F14 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
F16 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
F17 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 4/22( 18%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 18/22( 81%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 45/141 ( 31%)
Total logic cells used: 202/1728 ( 11%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.56/4 ( 89%)
Total fan-in: 721/6912 ( 10%)
Total input pins required: 40
Total input I/O cell registers required: 0
Total output pins required: 11
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 202
Total flipflops required: 5
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 45/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 7 0 8 8 0 6 7 3 8 5 6 8 8 6 6 8 8 107/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 24/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 8 8 0 0 1 7 8 8 8 0 8 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71/0
Total: 0 0 0 0 0 8 8 0 0 1 7 8 8 8 0 8 7 8 0 5 15 0 8 8 0 6 7 3 8 5 6 8 8 14 14 8 8 202/0
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