library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;

entity testram is
  port ( CLKIN, WE,x,y: in STD_LOGIC;
	      hs,vs: out std_logic;
		   R : out std_logic_vector(2 downto 0);
        G : out std_logic_vector(2 downto 0);
        B : out std_logic_vector(1 downto 0);
        DOUT: out STD_LOGIC_VECTOR (7 downto 0);
        CLKOUT: out std_logic );
end testram;

architecture testram_arch of testram is
signal logic1: std_logic;
signal vga_r,vga_g,vga_b: std_logic;
signal Q: std_logic_vector(31 downto 0);
signal ADDR: std_logic_vector(3 downto 0);
signal DIN: std_logic_vector(7 downto 0);
signal DO: std_logic_vector(7 downto 0);
signal innum,innum0: std_logic_vector(15 downto 0);
signal innum1,innum2,innum3,innum4: std_logic_vector( 6 downto 0);

component vga_16
	 Port ( clk : in std_logic;
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic;
		      innum  : in std_logic_vector(15 downto 0);
		      innum0 : in std_logic_vector(15 downto 0); 
           innum1 : in std_logic_vector(6 downto 0);
           innum2 : in std_logic_vector(6 downto 0);
           innum3 : in std_logic_vector(6 downto 0);
		   innum4 : in std_logic_vector(6 downto 0));
end component;

component RAMB4_S8
port (	address		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		clken		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end component;

begin
logic1 <= '1';
U0: vga_16 port map(clkin, hs, vs, vga_r,vga_g,vga_b,innum,innum0,innum1,innum2,innum3,innum4);
	R(0)<=vga_r;
	R(1)<=vga_r;
	R(2)<=vga_r;
	G(0)<=vga_g;
	G(1)<=vga_g;
	G(2)<=vga_g;
	B(0)<=vga_b;
	B(1)<=vga_b;
innum0<="00000000"& DO;
innum<="000000000000"& addr;

process(CLKIN)
BEGIN
IF (CLKIN'EVENT AND CLKIN='1') THEN
  Q <= Q + 1 ;
END IF;  
END PROCESS;
CLKOUT <= Q(22);
ADDR <= Q(30 DOWNTO 27);

process(x,y)
BEGIN
	if x='0'
	  then DIN <="01010101";
	elsif y='0'
	  then DIN <="10101010";
	else
	  DIN <="10101011";
	end if;	
END PROCESS;

ram0: RAMB4_S8
port map (address=>ADDR,clken=>logic1,clock=>CLKIN,data=>DIN,wren=>WE,q=>DO);
 DOUT<= DO;				--not DO;
--HEX-to-seven-segment decoder
--   HEX:   in    STD_LOGIC_VECTOR (3 downto 0);
--   LED:   out   STD_LOGIC_VECTOR (6 downto 0);
    with DO(7 downto 4) SELect
   innum4<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
 	 with DO(3 downto 0) SELect
   innum3<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
	 with DO(7 downto 4) SELect
   innum2<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
	 with DO(3 downto 0) SELect
   innum1<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
end testram_arch;