?? ccd.tan.qmsg
字號(hào):
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:H_COUNTER_rtl_1\|dffs\[1\] register STATE\[0\] 31.45 MHz 31.8 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 31.45 MHz between source register \"lpm_counter:H_COUNTER_rtl_1\|dffs\[1\]\" and destination register \"STATE\[0\]\" (period= 31.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.800 ns + Longest register register " "Info: + Longest register to register delay is 19.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:H_COUNTER_rtl_1\|dffs\[1\] 1 REG LC34 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 17; REG Node = 'lpm_counter:H_COUNTER_rtl_1\|dffs\[1\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:H_COUNTER_rtl_1|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns LessThan0~71sexp3 2 COMB SEXP17 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'LessThan0~71sexp3'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:H_COUNTER_rtl_1|dffs[1] LessThan0~71sexp3 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 11.000 ns STATE~1739 3 COMB LC17 1 " "Info: 3: + IC(0.000 ns) + CELL(5.000 ns) = 11.000 ns; Loc. = LC17; Fanout = 1; COMB Node = 'STATE~1739'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { LessThan0~71sexp3 STATE~1739 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 13.800 ns STATE~1716 4 COMB LC18 1 " "Info: 4: + IC(0.000 ns) + CELL(2.800 ns) = 13.800 ns; Loc. = LC18; Fanout = 1; COMB Node = 'STATE~1716'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { STATE~1739 STATE~1716 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 19.800 ns STATE\[0\] 5 REG LC4 78 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 19.800 ns; Loc. = LC4; Fanout = 78; REG Node = 'STATE\[0\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STATE~1716 STATE[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.800 ns ( 89.90 % ) " "Info: Total cell delay = 17.800 ns ( 89.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 10.10 % ) " "Info: Total interconnect delay = 2.000 ns ( 10.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "19.800 ns" { lpm_counter:H_COUNTER_rtl_1|dffs[1] LessThan0~71sexp3 STATE~1739 STATE~1716 STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "19.800 ns" { lpm_counter:H_COUNTER_rtl_1|dffs[1] LessThan0~71sexp3 STATE~1739 STATE~1716 STATE[0] } { 0.000ns 1.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 5.000ns 5.000ns 2.800ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.000 ns - Smallest " "Info: - Smallest clock skew is -8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns STATE\[0\] 2 REG LC4 78 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 78; REG Node = 'STATE\[0\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK STATE[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out STATE[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 9.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns P_CNT 2 REG LC65 14 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC65; Fanout = 14; REG Node = 'P_CNT'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { CLK P_CNT } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns lpm_counter:H_COUNTER_rtl_1\|dffs\[1\] 3 REG LC34 17 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC34; Fanout = 17; REG Node = 'lpm_counter:H_COUNTER_rtl_1\|dffs\[1\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK CLK~out P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out STATE[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK CLK~out P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 35 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "19.800 ns" { lpm_counter:H_COUNTER_rtl_1|dffs[1] LessThan0~71sexp3 STATE~1739 STATE~1716 STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "19.800 ns" { lpm_counter:H_COUNTER_rtl_1|dffs[1] LessThan0~71sexp3 STATE~1739 STATE~1716 STATE[0] } { 0.000ns 1.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 5.000ns 5.000ns 2.800ns 5.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out STATE[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { CLK P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { CLK CLK~out P_CNT lpm_counter:H_COUNTER_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "ADS register STATE_OUT\[1\]~reg0 register STATE_OUT\[1\]~reg0 100.0 MHz 10.0 ns Internal " "Info: Clock \"ADS\" has Internal fmax of 100.0 MHz between source register \"STATE_OUT\[1\]~reg0\" and destination register \"STATE_OUT\[1\]~reg0\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATE_OUT\[1\]~reg0 1 REG LC64 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC64; Fanout = 3; REG Node = 'STATE_OUT\[1\]~reg0'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATE_OUT[1]~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 74 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns STATE_OUT\[1\]~reg0 2 REG LC64 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC64; Fanout = 3; REG Node = 'STATE_OUT\[1\]~reg0'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STATE_OUT[1]~reg0 STATE_OUT[1]~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 74 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STATE_OUT[1]~reg0 STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { STATE_OUT[1]~reg0 STATE_OUT[1]~reg0 } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADS destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"ADS\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ADS 1 CLK PIN_20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_20; Fanout = 2; CLK Node = 'ADS'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADS } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns STATE_OUT\[1\]~reg0 2 REG LC64 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC64; Fanout = 3; REG Node = 'STATE_OUT\[1\]~reg0'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 74 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADS source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"ADS\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ADS 1 CLK PIN_20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_20; Fanout = 2; CLK Node = 'ADS'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADS } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns STATE_OUT\[1\]~reg0 2 REG LC64 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC64; Fanout = 3; REG Node = 'STATE_OUT\[1\]~reg0'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 74 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 74 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 74 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STATE_OUT[1]~reg0 STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { STATE_OUT[1]~reg0 STATE_OUT[1]~reg0 } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "STATE\[0\] RUN CLK 15.000 ns register " "Info: tsu for register \"STATE\[0\]\" (data pin = \"RUN\", clock pin = \"CLK\") is 15.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest pin register " "Info: + Longest pin to register delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RUN 1 PIN PIN_30 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_30; Fanout = 2; PIN Node = 'RUN'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { RUN } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.500 ns STATE~1716 2 COMB LC18 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC18; Fanout = 1; COMB Node = 'STATE~1716'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RUN STATE~1716 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns STATE\[0\] 3 REG LC4 78 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC4; Fanout = 78; REG Node = 'STATE\[0\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STATE~1716 STATE[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.500 ns ( 86.21 % ) " "Info: Total cell delay = 12.500 ns ( 86.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 13.79 % ) " "Info: Total interconnect delay = 2.000 ns ( 13.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { RUN STATE~1716 STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { RUN RUN~out STATE~1716 STATE[0] } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 35 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns STATE\[0\] 2 REG LC4 78 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 78; REG Node = 'STATE\[0\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK STATE[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out STATE[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { RUN STATE~1716 STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { RUN RUN~out STATE~1716 STATE[0] } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 5.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK STATE[0] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out STATE[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SRG1 SRG2~reg0 13.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"SRG1\" through register \"SRG2~reg0\" is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns SRG2~reg0 2 REG LC49 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC49; Fanout = 2; REG Node = 'SRG2~reg0'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK SRG2~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 115 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK SRG2~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out SRG2~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 115 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register pin " "Info: + Longest register to pin delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SRG2~reg0 1 REG LC49 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC49; Fanout = 2; REG Node = 'SRG2~reg0'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRG2~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 115 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns SRG2~2 2 COMB LC77 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC77; Fanout = 1; COMB Node = 'SRG2~2'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { SRG2~reg0 SRG2~2 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 9.500 ns SRG1 3 PIN PIN_51 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'SRG1'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { SRG2~2 SRG1 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監(jiān)視系統(tǒng)/CCD_VHDL/CCD.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { SRG2~reg0 SRG2~2 SRG1 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { SRG2~reg0 SRG2~2 SRG1 } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK SRG2~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out SRG2~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { SRG2~reg0 SRG2~2 SRG1 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { SRG2~reg0 SRG2~2 SRG1 } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
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