{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 12 -1 0 } } { "d:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ADS " "Info: Assuming node \"ADS\" is an undefined clock" {  } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 13 -1 0 } } { "d:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "ADS" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "L_CNT " "Info: Detected ripple clock \"L_CNT\" as buffer" {  } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 19 -1 0 } } { "d:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "L_CNT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "P_CNT " "Info: Detected ripple clock \"P_CNT\" as buffer" {  } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 19 -1 0 } } { "d:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "P_CNT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}