{ "Info" "ITDB_TH_RESULT" "STATE_OUT\[1\]~reg0 PIXEL ADS 3.000 ns register " "Info: th for register \"STATE_OUT\[1\]~reg0\" (data pin = \"PIXEL\", clock pin = \"ADS\") is 3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADS destination 6.500 ns + Longest register " "Info: + Longest clock path from clock \"ADS\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ADS 1 CLK PIN_20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_20; Fanout = 2; CLK Node = 'ADS'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADS } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns STATE_OUT\[1\]~reg0 2 REG LC64 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC64; Fanout = 3; REG Node = 'STATE_OUT\[1\]~reg0'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 74 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 74 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns PIXEL 1 PIN PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_28; Fanout = 10; PIN Node = 'PIXEL'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { PIXEL } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns STATE_OUT\[1\]~reg0 2 REG LC64 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC64; Fanout = 3; REG Node = 'STATE_OUT\[1\]~reg0'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { PIXEL STATE_OUT[1]~reg0 } "NODE_NAME" } } { "CCD.vhd" "" { Text "D:/MyProject/2米4攝譜儀狹縫監視系統/CCD_VHDL/CCD.vhd" 74 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { PIXEL STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { PIXEL PIXEL~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { ADS STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { ADS ADS~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { PIXEL STATE_OUT[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { PIXEL PIXEL~out STATE_OUT[1]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 23 15:33:22 2008 " "Info: Processing ended: Tue Sep 23 15:33:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}