?? ccd.tan.rpt
字號(hào):
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM7128SLC84-10 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; ADS ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[1] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[0] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[3] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[2] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[8] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[7] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[6] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[5] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[4] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[5] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[4] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[3] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[2] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[1] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[0] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[6] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[7] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:V_COUNTER_rtl_0|dffs[8] ; STATE[0] ; CLK ; CLK ; None ; None ; 19.800 ns ;
; N/A ; 38.46 MHz ( period = 26.000 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[1] ; STATE[1] ; CLK ; CLK ; None ; None ; 14.000 ns ;
; N/A ; 38.46 MHz ( period = 26.000 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[0] ; STATE[1] ; CLK ; CLK ; None ; None ; 14.000 ns ;
; N/A ; 38.46 MHz ( period = 26.000 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[3] ; STATE[1] ; CLK ; CLK ; None ; None ; 14.000 ns ;
; N/A ; 38.46 MHz ( period = 26.000 ns ) ; lpm_counter:H_COUNTER_rtl_1|dffs[2] ; STATE[1] ; CLK ; CLK ; None ; None ; 14.000 ns ;
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