{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "h1_over " "Info: Detected ripple clock \"h1_over\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 33 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "h1_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "m2_over " "Info: Detected ripple clock \"m2_over\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 32 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "m2_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "m1_over " "Info: Detected ripple clock \"m1_over\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 31 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "m1_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "S2_over " "Info: Detected ripple clock \"S2_over\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 30 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "S2_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "s1_over " "Info: Detected ripple clock \"s1_over\" as buffer" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 29 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "s1_over" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:div_cnt_rtl_0\|dffs\[20\] " "Info: Detected ripple clock \"lpm_counter:div_cnt_rtl_0\|dffs\[20\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:div_cnt_rtl_0\|dffs\[20\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register h2_cnt\[1\] register data4\[1\] 14.71 MHz 68.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 14.71 MHz between source register \"h2_cnt\[1\]\" and destination register \"data4\[1\]\" (period= 68.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns h2_cnt\[1\] 1 REG LC34 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'h2_cnt\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { h2_cnt[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns Select~277 2 COMB LC3 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'Select~277'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { h2_cnt[1] Select~277 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns data4\[1\] 3 REG LC4 22 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC4; Fanout = 22; REG Node = 'data4\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "1.000 ns" { Select~277 data4[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { h2_cnt[1] Select~277 data4[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { h2_cnt[1] Select~277 data4[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-54.000 ns - Smallest " "Info: - Smallest clock skew is -54.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns data4\[1\] 2 REG LC4 22 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 22; REG Node = 'data4\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "0.000 ns" { clk data4[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "3.000 ns" { clk data4[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out data4[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 57.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 57.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[20\] 2 REG LC113 6 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC113; Fanout = 6; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[20\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "1.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns s1_over 3 REG LC11 4 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC11; Fanout = 4; REG Node = 's1_over'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] s1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns S2_over 4 REG LC16 5 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC16; Fanout = 5; REG Node = 'S2_over'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { s1_over S2_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns m1_over 5 REG LC23 4 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC23; Fanout = 4; REG Node = 'm1_over'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { S2_over m1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 40.000 ns m2_over 6 REG LC7 5 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'm2_over'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { m1_over m2_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 49.000 ns h1_over 7 REG LC42 2 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC42; Fanout = 2; REG Node = 'h1_over'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { m2_over h1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 57.000 ns h2_cnt\[1\] 8 REG LC34 7 " "Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 57.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'h2_cnt\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "45.000 ns 78.95 % " "Info: Total cell delay = 45.000 ns ( 78.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.000 ns 21.05 % " "Info: Total interconnect delay = 12.000 ns ( 21.05 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "57.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "57.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "3.000 ns" { clk data4[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out data4[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "57.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "57.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { h2_cnt[1] Select~277 data4[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { h2_cnt[1] Select~277 data4[1] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "3.000 ns" { clk data4[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out data4[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "57.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "57.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } }  } 0}