?? clock.tan.qmsg
字號:
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "h1_cnt\[1\] h2_cnt\[1\] clk 4.0 ns " "Info: Found hold time violation between source pin or register \"h1_cnt\[1\]\" and destination pin or register \"h2_cnt\[1\]\" for clock \"clk\" (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.000 ns + Largest " "Info: + Largest clock skew is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 57.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 57.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[20\] 2 REG LC113 6 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC113; Fanout = 6; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[20\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "1.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns s1_over 3 REG LC11 4 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC11; Fanout = 4; REG Node = 's1_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] s1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns S2_over 4 REG LC16 5 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC16; Fanout = 5; REG Node = 'S2_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { s1_over S2_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns m1_over 5 REG LC23 4 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC23; Fanout = 4; REG Node = 'm1_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { S2_over m1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 40.000 ns m2_over 6 REG LC7 5 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'm2_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { m1_over m2_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 49.000 ns h1_over 7 REG LC42 2 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC42; Fanout = 2; REG Node = 'h1_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { m2_over h1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 33 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 57.000 ns h2_cnt\[1\] 8 REG LC34 7 " "Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 57.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'h2_cnt\[1\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "45.000 ns 78.95 % " "Info: Total cell delay = 45.000 ns ( 78.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.000 ns 21.05 % " "Info: Total interconnect delay = 12.000 ns ( 21.05 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "57.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "57.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } { 0.0ns 0.0ns 0.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 7.0ns 7.0ns 7.0ns 7.0ns 7.0ns 6.0ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 48.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 48.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[20\] 2 REG LC113 6 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC113; Fanout = 6; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[20\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "1.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns s1_over 3 REG LC11 4 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC11; Fanout = 4; REG Node = 's1_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] s1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns S2_over 4 REG LC16 5 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC16; Fanout = 5; REG Node = 'S2_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { s1_over S2_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns m1_over 5 REG LC23 4 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC23; Fanout = 4; REG Node = 'm1_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { S2_over m1_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 40.000 ns m2_over 6 REG LC7 5 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'm2_over'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { m1_over m2_over } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 48.000 ns h1_cnt\[1\] 7 REG LC40 16 " "Info: 7: + IC(2.000 ns) + CELL(6.000 ns) = 48.000 ns; Loc. = LC40; Fanout = 16; REG Node = 'h1_cnt\[1\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { m2_over h1_cnt[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "38.000 ns 79.17 % " "Info: Total cell delay = 38.000 ns ( 79.17 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.000 ns 20.83 % " "Info: Total interconnect delay = 10.000 ns ( 20.83 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "48.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "48.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_cnt[1] } { 0.0ns 0.0ns 0.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 7.0ns 7.0ns 7.0ns 7.0ns 6.0ns } } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "57.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "57.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } { 0.0ns 0.0ns 0.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 7.0ns 7.0ns 7.0ns 7.0ns 7.0ns 6.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "48.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "48.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_cnt[1] } { 0.0ns 0.0ns 0.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 7.0ns 7.0ns 7.0ns 7.0ns 6.0ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" { } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns h1_cnt\[1\] 1 REG LC40 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC40; Fanout = 16; REG Node = 'h1_cnt\[1\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { h1_cnt[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns h2_cnt\[1\] 2 REG LC34 7 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'h2_cnt\[1\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { h1_cnt[1] h2_cnt[1] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { h1_cnt[1] h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { h1_cnt[1] h2_cnt[1] } { 0.0ns 2.0ns } { 0.0ns 6.0ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "57.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "57.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_over h2_cnt[1] } { 0.0ns 0.0ns 0.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 7.0ns 7.0ns 7.0ns 7.0ns 7.0ns 6.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "48.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "48.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] s1_over S2_over m1_over m2_over h1_cnt[1] } { 0.0ns 0.0ns 0.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 7.0ns 7.0ns 7.0ns 7.0ns 6.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "8.000 ns" { h1_cnt[1] h2_cnt[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { h1_cnt[1] h2_cnt[1] } { 0.0ns 2.0ns } { 0.0ns 6.0ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[7\] data4\[3\] 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[7\]\" through register \"data4\[3\]\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns data4\[3\] 2 REG LC19 20 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC19; Fanout = 20; REG Node = 'data4\[3\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "0.000 ns" { clk data4[3] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "3.000 ns" { clk data4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out data4[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data4\[3\] 1 REG LC19 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 20; REG Node = 'data4\[3\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "" { data4[3] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Mux~1492 2 COMB LC88 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC88; Fanout = 1; COMB Node = 'Mux~1492'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "9.000 ns" { data4[3] Mux~1492 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns dataout\[7\] 3 PIN PIN_57 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dataout\[7\]'" { } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "4.000 ns" { Mux~1492 dataout[7] } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "13.000 ns" { data4[3] Mux~1492 dataout[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { data4[3] Mux~1492 dataout[7] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } } } 0} } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "3.000 ns" { clk data4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out data4[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/" "" "13.000 ns" { data4[3] Mux~1492 dataout[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { data4[3] Mux~1492 dataout[7] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 14:26:46 2005 " "Info: Processing ended: Wed Nov 23 14:26:46 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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