{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 23 14:26:33 2005 " "Info: Processing started: Wed Nov 23 14:26:33 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-arch " "Info: Found design unit 1: clock-arch" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "clock.vhd(166) " "Info: VHDL Case Statement information at clock.vhd(166): OTHERS choice is never selected" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 166 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "clock.vhd(226) " "Info: VHDL Case Statement information at clock.vhd(226): OTHERS choice is never selected" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 226 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "div_cnt\[0\]~0 21 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=21) from the following logic: \"div_cnt\[0\]~0\"" {  } { { "clock.vhd" "div_cnt\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 18 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 19 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 20 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 28 -1 0 } } { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 27 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "clock.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/綜合實驗/數字時鐘/clock/clock.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "87 " "Info: Implemented 87 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "69 " "Info: Implemented 69 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 14:26:37 2005 " "Info: Processing ended: Wed Nov 23 14:26:37 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}