{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 16:39:20 2006 " "Info: Processing started: Fri Oct 20 16:39:20 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[1\] c\[4\] 13.507 ns Longest " "Info: Longest tpd from source pin \"b\[1\]\" to destination pin \"c\[4\]\" is 13.507 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns b\[1\] 1 PIN PIN_238 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_238; Fanout = 1; PIN Node = 'b\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmp" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/db/cmp.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/" "" "" { b[1] } "NODE_NAME" } "" } } { "cmp.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/cmp.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.345 ns) + CELL(0.292 ns) 7.112 ns LessThan~349 2 COMB LC_X4_Y20_N4 1 " "Info: 2: + IC(5.345 ns) + CELL(0.292 ns) = 7.112 ns; Loc. = LC_X4_Y20_N4; Fanout = 1; COMB Node = 'LessThan~349'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmp" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/db/cmp.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/" "" "5.637 ns" { b[1] LessThan~349 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.292 ns) 7.843 ns LessThan~350 3 COMB LC_X4_Y20_N5 1 " "Info: 3: + IC(0.439 ns) + CELL(0.292 ns) = 7.843 ns; Loc. = LC_X4_Y20_N5; Fanout = 1; COMB Node = 'LessThan~350'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmp" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/db/cmp.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/" "" "0.731 ns" { LessThan~349 LessThan~350 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.114 ns) 8.373 ns LessThan~351 4 COMB LC_X4_Y20_N2 4 " "Info: 4: + IC(0.416 ns) + CELL(0.114 ns) = 8.373 ns; Loc. = LC_X4_Y20_N2; Fanout = 4; COMB Node = 'LessThan~351'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmp" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/db/cmp.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/" "" "0.530 ns" { LessThan~350 LessThan~351 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.026 ns) + CELL(2.108 ns) 13.507 ns c\[4\] 5 PIN PIN_202 0 " "Info: 5: + IC(3.026 ns) + CELL(2.108 ns) = 13.507 ns; Loc. = PIN_202; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmp" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/db/cmp.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/" "" "5.134 ns" { LessThan~351 c[4] } "NODE_NAME" } "" } } { "cmp.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/cmp.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.281 ns ( 31.69 % ) " "Info: Total cell delay = 4.281 ns ( 31.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.226 ns ( 68.31 % ) " "Info: Total interconnect delay = 9.226 ns ( 68.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmp" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/db/cmp.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗/四位比較器/" "" "13.507 ns" { b[1] LessThan~349 LessThan~350 LessThan~351 c[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.507 ns" { b[1] b[1]~out0 LessThan~349 LessThan~350 LessThan~351 c[4] } { 0.000ns 0.000ns 5.345ns 0.439ns 0.416ns 3.026ns } { 0.000ns 1.475ns 0.292ns 0.292ns 0.114ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:39:20 2006 " "Info: Processing ended: Fri Oct 20 16:39:20 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}