{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 16:39:13 2006 " "Info: Processing started: Fri Oct 20 16:39:13 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cmp -c cmp " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cmp -c cmp" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cmp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cmp.v" { { "Info" "ISGN_ENTITY_NAME" "1 cmp " "Info: Found entity 1: cmp" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cmp " "Info: Elaborating entity \"cmp\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "c\[1\] VCC " "Warning: Pin \"c\[1\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "c\[5\] GND " "Warning: Pin \"c\[5\]\" stuck at GND" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "c\[6\] GND " "Warning: Pin \"c\[6\]\" stuck at GND" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] VCC " "Warning: Pin \"en\[1\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] VCC " "Warning: Pin \"en\[2\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] VCC " "Warning: Pin \"en\[3\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] VCC " "Warning: Pin \"en\[4\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] VCC " "Warning: Pin \"en\[5\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] VCC " "Warning: Pin \"en\[6\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] VCC " "Warning: Pin \"en\[7\]\" stuck at VCC" {  } { { "cmp.v" "" { Text "E:/揚創開發板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎實驗/四位比較器/cmp.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "27 " "Info: Implemented 27 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "3 " "Info: Implemented 3 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:39:13 2006 " "Info: Processing ended: Fri Oct 20 16:39:13 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}