{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 16:18:10 2006 " "Info: Processing started: Fri Oct 20 16:18:10 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[2\] c\[2\] 15.612 ns Longest " "Info: Longest tpd from source pin \"b\[2\]\" to destination pin \"c\[2\]\" is 15.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns b\[2\] 1 PIN PIN_238 6 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_238; Fanout = 6; PIN Node = 'b\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "" { b[2] } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/div.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.070 ns) + CELL(0.442 ns) 7.987 ns c_tmp\[0\]~454 2 COMB LC_X12_Y20_N1 2 " "Info: 2: + IC(6.070 ns) + CELL(0.442 ns) = 7.987 ns; Loc. = LC_X12_Y20_N1; Fanout = 2; COMB Node = 'c_tmp\[0\]~454'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "6.512 ns" { b[2] c_tmp[0]~454 } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/div.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.590 ns) 9.047 ns c_tmp\[0\]~456 3 COMB LC_X12_Y20_N8 1 " "Info: 3: + IC(0.470 ns) + CELL(0.590 ns) = 9.047 ns; Loc. = LC_X12_Y20_N8; Fanout = 1; COMB Node = 'c_tmp\[0\]~456'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "1.060 ns" { c_tmp[0]~454 c_tmp[0]~456 } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/div.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.442 ns) 9.893 ns c_tmp\[0\]~458 4 COMB LC_X12_Y20_N7 6 " "Info: 4: + IC(0.404 ns) + CELL(0.442 ns) = 9.893 ns; Loc. = LC_X12_Y20_N7; Fanout = 6; COMB Node = 'c_tmp\[0\]~458'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "0.846 ns" { c_tmp[0]~456 c_tmp[0]~458 } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/div.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.442 ns) 11.167 ns reduce_or~740 5 COMB LC_X13_Y20_N3 1 " "Info: 5: + IC(0.832 ns) + CELL(0.442 ns) = 11.167 ns; Loc. = LC_X13_Y20_N3; Fanout = 1; COMB Node = 'reduce_or~740'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "1.274 ns" { c_tmp[0]~458 reduce_or~740 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.337 ns) + CELL(2.108 ns) 15.612 ns c\[2\] 6 PIN PIN_200 0 " "Info: 6: + IC(2.337 ns) + CELL(2.108 ns) = 15.612 ns; Loc. = PIN_200; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "4.445 ns" { reduce_or~740 c[2] } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/div.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.499 ns ( 35.22 % ) " "Info: Total cell delay = 5.499 ns ( 35.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.113 ns ( 64.78 % ) " "Info: Total interconnect delay = 10.113 ns ( 64.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "div" "UNKNOWN" "V1" "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/db/div.quartus_db" { Floorplan "E:/揚(yáng)創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/除法器/" "" "15.612 ns" { b[2] c_tmp[0]~454 c_tmp[0]~456 c_tmp[0]~458 reduce_or~740 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.612 ns" { b[2] b[2]~out0 c_tmp[0]~454 c_tmp[0]~456 c_tmp[0]~458 reduce_or~740 c[2] } { 0.000ns 0.000ns 6.070ns 0.470ns 0.404ns 0.832ns 2.337ns } { 0.000ns 1.475ns 0.442ns 0.590ns 0.442ns 0.442ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:18:11 2006 " "Info: Processing ended: Fri Oct 20 16:18:11 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}