?? div.asm.rpt
字號:
Assembler report for div
Fri Oct 20 16:18:10 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: E:/揚創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實驗/除法器/div.sof
6. Assembler Device Options: E:/揚創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實驗/除法器/div.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Oct 20 16:18:10 2006 ;
; Revision Name ; div ;
; Top-level Entity Name ; div ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
+-----------------------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+--------------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+----------+---------------+
; Configuration device ; Epcs1 ; Auto ;
; Use smart compilation ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; JTAG user code for target device ; Ffffffff ; Ffffffff ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; JTAG user code for configuration device ; Ffffffff ; Ffffffff ;
; Configuration device auto user code ; Off ; Off ;
; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
+--------------------------------------------------------------------------------+----------+---------------+
+---------------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------------+
; E:/揚創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實驗/除法器/div.sof ;
; E:/揚創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實驗/除法器/div.pof ;
+---------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Assembler Device Options: E:/揚創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實驗/除法器/div.sof ;
+----------------+------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------------------+
; Device ; EP1C6Q240C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x00090D7D ;
+----------------+------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Assembler Device Options: E:/揚創(chuàng)開發(fā)板/Mars-EDA-P/EP1C12/示例程序/veriloge/基礎(chǔ)實驗/除法器/div.pof ;
+----------------+------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------------------+
; Device ; EPCS1 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x0163CA13 ;
+----------------+------------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 16:18:09 2006
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off div -c div
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Oct 20 16:18:10 2006
Info: Elapsed time: 00:00:01
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