{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 09 15:05:35 2008 " "Info: Processing started: Tue Dec 09 15:05:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off mux -c mux " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mux -c mux" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "mux EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"mux\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_TOP" "" "Info: Selected Migration Device List" { { "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_SUB" "EP1C12Q240C8 " "Info: Selected EP1C12Q240C8 for migration" {  } {  } 0 0 "Selected %1!s! for migration" 0 0}  } {  } 0 0 "Selected Migration Device List" 0 0}
{ "Info" "IMPP_MPP_NUM_MIGRATABLE_IO" "227 " "Info: Selected migration device list is legal with 227 total of migratable pins" {  } {  } 0 0 "Selected migration device list is legal with %1!d! total of migratable pins" 0 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 0 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0}
{ "Info" "IFYGR_FYGR_MIGRATION_PIN_CANNOT_BE_USED_AS" "12 regular " "Info: Selected device migration path cannot use 12 pins as \"regular\" I/Os" { { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "80 " "Info: Pin \"80\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "81 " "Info: Pin \"81\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "96 " "Info: Pin \"96\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "97 " "Info: Pin \"97\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "102 " "Info: Pin \"102\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "103 " "Info: Pin \"103\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "198 " "Info: Pin \"198\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "199 " "Info: Pin \"199\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "204 " "Info: Pin \"204\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "205 " "Info: Pin \"205\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "220 " "Info: Pin \"220\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "221 " "Info: Pin \"221\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0}  } {  } 2 0 "Selected device migration path cannot use %1!d! pins as \"%2!s!\" I/Os" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 25 " "Info: No exact pin location assignment(s) for 1 pins of 25 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a " "Info: Pin a not assigned to an exact location on the device" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 9 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { a } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { a } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}