{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 1 0 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 42 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 24 24 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 24 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[0\] VCC " "Info: Pin d\[0\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 12 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[0\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { d[0] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { d[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[0\] GND " "Info: Pin en\[0\] has GND driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[0\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[0] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[1\] VCC " "Info: Pin en\[1\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[1\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[1] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[2\] VCC " "Info: Pin en\[2\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[2\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[2] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[3\] VCC " "Info: Pin en\[3\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[3\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[3] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[4\] VCC " "Info: Pin en\[4\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[4\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[4] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[5\] VCC " "Info: Pin en\[5\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[5\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[5] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[6\] VCC " "Info: Pin en\[6\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[6\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[6] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[7\] VCC " "Info: Pin en\[7\] has VCC driving its datain port" {  } { { "mux.v" "" { Text "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.v" 14 -1 0 } } { "e:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en\[7\]" } } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/db/mux.quartus_db" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/" "" "" { en[7] } "NODE_NAME" } "" } } { "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" { Floorplan "E:/FPGA學習板資料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套試驗例程及相關試驗指導/示例程序/verilog/基礎實驗/多路選擇器/mux.fld" "" "" { en[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 09 15:05:43 2008 " "Info: Processing ended: Tue Dec 09 15:05:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}