Device-Specific Information:                       d:\mydesign\shift\shift.rpt
shift

** EQUATIONS **

CP       : INPUT;
DI       : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
D4       : INPUT;
D5       : INPUT;
D6       : INPUT;
D7       : INPUT;
LD       : INPUT;
Rd       : INPUT;

-- Node name is 'DO' 
-- Equation name is 'DO', type is output 
DO       =  _LC6_D27;

-- Node name is ':22' = 'QN0' 
-- Equation name is 'QN0', location is LC8_D22, type is buried.
QN0      = DFFE( _EQ001, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ001 =  D0 & !LD
         #  DI &  LD;

-- Node name is ':23' = 'QN1' 
-- Equation name is 'QN1', location is LC1_D27, type is buried.
QN1      = DFFE( _EQ002, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ002 =  LD &  QN0
         #  D1 & !LD;

-- Node name is ':24' = 'QN2' 
-- Equation name is 'QN2', location is LC2_D27, type is buried.
QN2      = DFFE( _EQ003, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ003 =  LD &  QN1
         #  D2 & !LD;

-- Node name is ':25' = 'QN3' 
-- Equation name is 'QN3', location is LC7_D27, type is buried.
QN3      = DFFE( _EQ004, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ004 =  LD &  QN2
         #  D3 & !LD;

-- Node name is ':26' = 'QN4' 
-- Equation name is 'QN4', location is LC8_D27, type is buried.
QN4      = DFFE( _EQ005, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ005 =  LD &  QN3
         #  D4 & !LD;

-- Node name is ':27' = 'QN5' 
-- Equation name is 'QN5', location is LC3_D27, type is buried.
QN5      = DFFE( _EQ006, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ006 =  LD &  QN4
         #  D5 & !LD;

-- Node name is ':28' = 'QN6' 
-- Equation name is 'QN6', location is LC4_D27, type is buried.
QN6      = DFFE( _EQ007, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ007 =  LD &  QN5
         #  D6 & !LD;

-- Node name is '~29~1' = 'QN7~1' 
-- Equation name is '~29~1', location is LC6_D27, type is buried.
-- synthesized logic cell 
_LC6_D27 = DFFE( _EQ008, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ008 =  LD &  QN6
         #  D7 & !LD;

-- Node name is ':29' = 'QN7' 
-- Equation name is 'QN7', location is LC5_D27, type is buried.
QN7      = DFFE( _EQ009, GLOBAL( CP), GLOBAL( Rd),  VCC,  VCC);
  _EQ009 =  LD &  QN6
         #  D7 & !LD;

-- Node name is 'Q0' 
-- Equation name is 'Q0', type is output 
Q0       =  QN0;

-- Node name is 'Q1' 
-- Equation name is 'Q1', type is output 
Q1       =  QN1;

-- Node name is 'Q2' 
-- Equation name is 'Q2', type is output 
Q2       =  QN2;

-- Node name is 'Q3' 
-- Equation name is 'Q3', type is output 
Q3       =  QN3;

-- Node name is 'Q4' 
-- Equation name is 'Q4', type is output 
Q4       =  QN4;

-- Node name is 'Q5' 
-- Equation name is 'Q5', type is output 
Q5       =  QN5;

-- Node name is 'Q6' 
-- Equation name is 'Q6', type is output 
Q6       =  QN6;

-- Node name is 'Q7' 
-- Equation name is 'Q7', type is output 
Q7       =  QN7;



Project Information                                d:\mydesign\shift\shift.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 25,205K