library ieee;
use ieee.std_logic_1164.all;

entity tb is
port(
	ck,htb,cmc,jh:		in std_logic;
	result:	out std_logic
	);
end tb;

architecture a of tb is

signal count: integer range 0 to 50000;
begin
process
	begin
		wait until ck = '1' ;
		if count <49999  then
			count <= count + 1;
		else
			count <= 0;
		end if;
	end process;

process(count)
	begin
	    if count <=199 then
			result<=cmc;
	    elsif count<=399 and count>=200 then
	       result<=jh;
	    elsif count<=24799 and count>=400 then
	       result<=htb;
	    elsif count<=24999 and count>=24800 then
	       result<=jh;
	    elsif count<=25199 and count>=25000 then
	       result<=cmc;
	    elsif count<=25399 and count>=25200 then
	       result<=jh;
	    elsif count<=49800 and count>=25400 then
	       result<=htb;
	    else 
	       result<=jh;
	  end if;
	end process;
end a;