module dma_all(               CLK,               LA,               LD,               LHOLD,               LHOLDA,               LWR,               READY_,               ADS_,               BLAST_,               RAM_D,               RAM_A,               RAM_CE1_,               RAM_CE2,               RAM_WE_,                              read_ram_start,               data_en,               data_input,               o_ram_data,               ram_data_buf,               LRESET_,               rd_7864_fifo,               rd_7301_fifo,               rd_12channel_io,               reset_by_hand_,               state,
               RAM_OE_,
               ///////
               ad7864_hf,
               ad7864_em,
               ad7301_hf,
               ad7301_em,
               ///////
               //core_controller模塊接口
               RHF_ONE_,
               RFE_ONE_,                  //422第一路fifo讀空
			   RD_FIFO_ONE,               //讀422第一路fifo控制信號
			   RHF_TWO_,                  //422第一路fifo半滿
			   RFE_TWO_,                  //422第二路fifo讀空
			   RD_FIFO_TWO,               //讀422第二路fifo控制信號
			   RHF_THREE_,                //422第二路fifo半滿
			   RFE_THREE_,
			   RD_FIFO_THREE,
			   RHF_FORE_,
			   RFE_FORE_,
			   RD_FIFO_FORE,
			   RHF_232_,
			   RFE_232_,
			   RD_FIFO_232,
			   operate_state,			   fifo_sel,		RAM_BHE_,RAM_BLE_,
		_9600_sel,_19200_sel,
		rd_232_ram               );//測試模塊，LA==13，觸發寫RAM模塊開始工作，再次觸發LA==13，寫RAM結束//LA==14，讀RAM開始，觸發DMA//LA==0，復位控制模塊// PCI LOCAL PINS block ==============================input CLK;input [9:2] LA;input LHOLD;input LWR;input ADS_;input BLAST_;input LRESET_;//_7864&_7301 input pinsinput ad7864_hf;input ad7864_em;input ad7301_hf;input ad7301_em;//communication(422&232) input pinsinput RHF_ONE_;                    //422第一路fifo半滿input RFE_ONE_;                    //422第一路fifo讀空input RHF_TWO_;input RFE_TWO_;input RHF_THREE_;input RFE_THREE_;input RHF_FORE_;input RFE_FORE_;input RHF_232_;input RFE_232_;//inout pinsinout [19:0] LD;inout [15:0] RAM_D;//communication(422&232) output pinsoutput RD_FIFO_ONE;                //讀422第一路fifo控制信號output RD_FIFO_TWO;output RD_FIFO_THREE;output RD_FIFO_FORE;output RD_FIFO_232;
output _9600_sel,_19200_sel;//DMA pinsoutput LHOLDA;output READY_;output reset_by_hand_;output [15:0] state;
output [4:0]fifo_sel;/*//core_controller pinsoutput RAM_CE1_VALID_;output RAM_CE2_VALID;output RAM_WE_VALID_;output [19:0] RAM_ADDR_VALID;*/output RAM_BHE_;output RAM_BLE_;//output sdramFifoWriteLock;//_7864&_7301&_12io control pinsoutput rd_7864_fifo;output rd_7301_fifo;output rd_12channel_io;
output rd_232_ram;//---------------------// RAM PINS  output[19:0] RAM_A;output RAM_CE1_;output RAM_CE2;output RAM_WE_;output RAM_OE_;output read_ram_start;output data_en;output data_input;output [15:0] o_ram_data;output [15:0] ram_data_buf;output [4:0] operate_state;///write_ram pins/*
output RAM_CE1_TEST_;output RAM_CE2_TEST;output RAM_WE_TEST_;output [19:0] RAM_A_TEST;output [15:0] RAM_D_TEST;
output RAM_BHE_TEST_;output RAM_BLE_TEST_;*////////////////////////////////////////////////////////wire RAM_CE1_VALID_;wire RAM_CE2_VALID;wire RAM_WE_VALID_;wire write_ram_start;wire read_ram_start;wire[19:0] LD;reg LHOLDA;reg READY_;wire rd_fifo;wire wr_fifo;wire rd_7864_fifo;wire rd_7301_fifo;wire rd_12channel_io;wire pci_read_ram;///////////////////////////////reg [19:0] RAM_A;reg [15:0]RAM_D;reg RAM_CE1_;reg RAM_CE2;reg RAM_WE_;//////////////////////////////wire RAM_BHE_;wire RAM_BLE_;wire data_en;wire data_input;wire [15:0] o_ram_data;wire [15:0] ram_data_buf;wire RAM_OE_;
wire [19:0] counter_output;
wire read_counter_ena;
wire read_state_ena;
wire [15:0] state;// Other internal variable ===wire reset_by_hand_;//wire reset_fifo;// write_ram input&output =======wire RAM_CE1_TEST_;wire RAM_CE2_TEST;wire RAM_WE_TEST_;wire RAM_BHE_TEST_;wire RAM_BLE_TEST_;wire [19:0] RAM_A_TEST;wire [15:0] RAM_D_TEST;//core_controller_input&output====wire RD_FIFO_ONE;wire RD_FIFO_TWO;wire RD_FIFO_THREE;wire RD_FIFO_FORE;wire RD_FIFO_232;wire busy_flag;wire [4:0] operate_state;wire [1:0] current_state_1;//此路為422讀寫ram模塊的當前狀態，不同于pci狀態控制的當前狀態wire D422_c1_fe;wire dma_finish_flag;wire [1:0] current_state;wire [19:0] RAM_ADDR_COUNTER_VALID;wire data_to_ram_en;wire data_to_ld_en;wire [19:0] RAM_ADDR_VALID;////////////////////////////////////////////////////////*assign RAM_A = (data_en | data_input)?RAM_A_TEST:20'hz;assign RAM_A = (data_to_ram_en|data_to_ld_en)?RAM_ADDR_VALID:20'hz;assign RAM_D = (data_en == 1'b1)?o_ram_data:20'hz;assign RAM_CE1_ = (data_en | data_input)?RAM_CE1_TEST_:1'b1;assign RAM_CE1_ = (data_to_ram_en|data_to_ld_en)?RAM_CE1_VALID_:1'b1;assign RAM_CE2 = (data_en | data_input)?RAM_CE2_TEST:1'b0;assign RAM_CE2 = (data_to_ram_en|data_to_ld_en)?RAM_CE2_VALID:1'b0;assign RAM_WE_ = (data_en | data_input)?RAM_WE_TEST_:1'b1;assign RAM_WE_ = (data_to_ram_en|data_to_ld_en)?RAM_WE_VALID_:1'b1;*/assign RAM_OE_ = 1'b0;always @(*)begin	if(data_to_ram_en|data_to_ld_en) RAM_A = RAM_ADDR_VALID;	else if(data_en | data_input)	RAM_A = RAM_A_TEST;	else RAM_A = 20'bz;		if(data_en == 1'b1)	RAM_D = o_ram_data;	else RAM_D = 20'hz;		if(data_to_ram_en|data_to_ld_en) RAM_CE1_ = RAM_CE1_VALID_;	else if(data_en | data_input)	RAM_CE1_ = RAM_CE1_TEST_;	else RAM_CE1_ = 1'b1;		if(data_to_ram_en|data_to_ld_en) RAM_CE2 = RAM_CE2_VALID;	else if(data_en | data_input)	RAM_CE2 = RAM_CE2_TEST;	else RAM_CE2 = 1'b1;		if(data_to_ram_en|data_to_ld_en) RAM_WE_ = RAM_WE_VALID_;	else if(data_en | data_input) RAM_WE_ = RAM_WE_TEST_;	else RAM_WE_ = 1'b1;end// pci interface block ==============================always @(posedge CLK)if (LHOLD)    LHOLDA =1'b1;else	LHOLDA =1'b0;reg [3:0] currentstate;reg [3:0] nextstate;parameter s0 = 4'd0, // idle           s1 = 4'd1, // cycle start          s2 = 4'd2, // single cycle wait state          s3 = 4'd3, // single cycle last state          s4 = 4'd4, // burst cycle wait state           s5 = 4'd5, // burst cycle repeat state           s6 = 4'd6; // burst cycle last statereg DATA_CTL_;always @ (*)casex (currentstate)s0: if (!ADS_  )     nextstate = s1;    else	nextstate = s0;s1: if (!BLAST_)    nextstate = s2;	else if (BLAST_)	nextstate = s4;	else 	nextstate = s1;s2: nextstate = s3;s3: if (!ADS_)	nextstate = s1;	else	nextstate = s0;						s4:	nextstate = s5;		s5:	if (BLAST_)	nextstate = s5;	else	nextstate = s6;s6:	if (!ADS_)    nextstate = s1;	else	nextstate = s0;endcasealways @ (currentstate)		casex(currentstate)s0: begin	READY_ =1'b1;	DATA_CTL_=1'b1;    ends1: begin	READY_ =1'b1;	DATA_CTL_=1'b1;	end	s2:	begin	READY_=1'b0;	DATA_CTL_=1'b0;	end	s3:	begin	READY_=1'b1;	DATA_CTL_=1'b1;	end	s4:	begin	READY_=1'b0;	DATA_CTL_=1'b0;	end	s5:	begin	READY_=1'b0;	DATA_CTL_=1'b0;	end	s6:	begin	READY_=1'b1;	DATA_CTL_=1'b1;	end	endcase	always @(posedge CLK)    currentstate <= nextstate;//reg [7:2] LA_BUF;/*always @ (posedge CLK)    LA_BUF <= LA;	*/	

assign state = {busy_flag,RHF_ONE_,RFE_ONE_,RHF_TWO_,RFE_TWO_,RHF_THREE_,RFE_THREE_,RHF_FORE_,RFE_FORE_,RHF_232_,RFE_232_,ad7864_hf,ad7864_em,ad7301_hf,ad7301_em};
assign LD = (data_input | read_ram_start)?(RAM_D):20'hz;
//assign LD = ( read_counter_ena )?/*counter_output*/(RAM_ADDR_COUNTER_VALID):16'hz;
assign LD = ( read_counter_ena )?/*counter_output*/{busy_flag,RAM_ADDR_COUNTER_VALID[18:0]}:20'hz;
assign LD = ( read_state_ena )?(state):20'hz;
assign reset_by_hand_=((LA[7:2]==6'b011111/*011_111 = 3_7*/)&&(READY_==1'b0))?1'b0:1'b1;//7c
assign pci_read_ram= ((LA[7:2]==6'b100001/*100_001 = 4_1*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//84
assign rd_7864_fifo= ((LA[7:2]==6'b110100/*110_100 = 6_4*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//D0 
assign rd_7301_fifo= ((LA[7:2]==6'b111011/*111_011 = 7_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//Ec 
assign rd_12channel_io= ((LA[7:2]==6'b001010/*001_010 = 1_2*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//28 
assign write_ram_start = ((LA[7:2]==6'b111000/*111_000 = 7_0*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//E0 
assign read_ram_start = ((LA[7:2]==6'b000111/*000_111 = 0_7*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//1F 
assign read_counter_ena = ((LA[7:2]==6'b101101/*101_101 = 5_5*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//B7 
assign read_state_ena = ((LA[7:2]==6'b110110/*110_110 = 6_6*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//DB assign dma_finish_flag = ((LA[7:2]==6'b101001/*100_001 = 4_1*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//a4//assign rd_422_ram_two= ((LA[7:2]==6'b100010/*100_010 = 4_2*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//88 //assign rd_422_ram_three= ((LA[7:2]==6'b100011/*100_011 = 4_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//8c //assign rd_422_ram_fore= ((LA[7:2]==6'b100100/*100_100 = 4_4*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//90 assign rd_232_ram= ((LA[7:2]==6'b010011/*010_011 = 2_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//4c //assign RESET_ = ((LA[5:2]==4'd15)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b0 : 1'b1; assign _9600_sel=((LA[7:2]==6'b010001)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b0 : 1'b1;//44
assign _19200_sel=((LA[7:2]==6'b010010)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b0 : 1'b1;//48///////////////////load submodule///////////////////////
write_ram write_ram(		.write_ram_start(write_ram_start),//input		.ram_addr(RAM_A_TEST),		.ram_data(RAM_D_TEST),                 //inout		.ram_ce1_(RAM_CE1_TEST_),		.ram_ce2(RAM_CE2_TEST),		.ram_we_(RAM_WE_TEST_),		.ram_bhe_(RAM_BHE_TEST_),		.ram_ble_(RAM_BLE_TEST_),		.read_ram_start(read_ram_start),//input		.CLK(CLK),                  //input		.reset_(reset_by_hand_),//input		//.LD(LD),                    //inout		.data_en(data_en),		.data_input(data_input),		.o_ram_data(o_ram_data),		.ram_data_buf(ram_data_buf),		.counter_output(counter_output));////////////////////////////////////////////////////////
///////////////load core_controller/////////////////////
core_controller core_controller(
        .RHF_ONE_(RHF_ONE_),//422_1
        .RFE_ONE_(RFE_ONE_),
        .RD_FIFO_ONE(RD_FIFO_ONE),
        .RHF_TWO_(RHF_TWO_),//422_2
        .RFE_TWO_(RFE_TWO_),
        .RD_FIFO_TWO(RD_FIFO_TWO),
        .RHF_THREE_(RHF_THREE_),//422_3
        .RFE_THREE_(RFE_THREE_),
        .RD_FIFO_THREE(RD_FIFO_THREE),
        .RHF_FORE_(RHF_FORE_),//422_4
		.RFE_FORE_(RFE_FORE_),
		.RD_FIFO_FORE(RD_FIFO_FORE),
		.RHF_232_(RHF_232_),//232
		.RFE_232_(RFE_232_),
		.RD_FIFO_232(RD_FIFO_232),
		.CLK(CLK),
		.reset_(reset_by_hand_),//input
		.busy_flag(busy_flag),
		.pci_read_flag(pci_read_ram),
		.operate_state(operate_state),
		.D422_c1_fe(D422_c1_fe),
		.dma_finish_flag(dma_finish_flag),//用來清零地址計數器//DMA結束標志，LA寫入該標志，表示此次DMA結束，清零地址寄存器
		.current_state(current_state_1),//此路為422讀寫ram模塊的當前狀態，不同于pci狀態控制的當前狀態
		.RAM_ADDR_COUNTER1(RAM_ADDR_COUNTER_VALID),
		.data_to_ram_en(data_to_ram_en),
		.data_to_ld_en(data_to_ld_en),
		.RAM_ADDR(RAM_ADDR_VALID),
		.RAM_CE1_(RAM_CE1_VALID_),
		.RAM_CE2(RAM_CE2_VALID),
		.RAM_BHE_(RAM_BHE_),
		.RAM_BLE_(RAM_BLE_),
		.RAM_WE_(RAM_WE_VALID_),		.fifo_sel(fifo_sel)
);//括號里面是頂層模塊
/////////////////////////////////////////////////////////*問題所在是RAM_ADDR,RAM_CE1_,RAM_CE2,RAM_BHE_,RAM_BLE_,RAM_WE_,RAM_OE_這幾個信號的連接分配問題*/////////////////////////////////////////////////////////endmodule