?? ad7301_controller.v
字號:
module ad7301_controller(reset_,
SCLK,
CLK_66M,
ad7301_channel,
sample_start,
fifo_usedw,
DOUT,
ad7301_data,
fifo_write,
state,
DIN
);
input reset_;
input CLK_66M;
input sample_start;
input [7:0] fifo_usedw;
input DOUT;
output SCLK;
reg SCLK;
output fifo_write;
reg fifo_write;
output [15:0] ad7301_data;
reg [15:0] ad7301_data;
output [15:0] state;
reg [15:0] state;
output DIN;
reg DIN;
output [2:0] ad7301_channel;
reg [2:0] ad7301_channel;
reg [15:0] ad7301_data_buf;
reg work_ena;
always @(posedge CLK_66M or negedge reset_)
begin
if(!reset_) begin
DIN <= 1'b0;
SCLK <= 1'b1;
ad7301_data <= 16'h0;
ad7301_data_buf <= 16'h0;
state <= 16'h0;
fifo_write <= 1'b0;
ad7301_channel <= 3'd7;
end
else begin
if(!sample_start) begin
case(state)
16'd0:begin
if(fifo_usedw[7] && fifo_usedw[6] && fifo_usedw[5]) begin
work_ena <= 1'b0;
end
else begin
work_ena <= 1'b1;
end
fifo_write <= 1'b0;
state <= state + 16'd1;
SCLK <= 1'b1;
ad7301_data <= 16'h0;
end
16'd66:begin
if(fifo_usedw[7] && fifo_usedw[6] && fifo_usedw[5]) begin
work_ena <= 1'b0;
state <= 16'd0;
end
else begin
work_ena <= 1'b1;
state <= state + 16'd1;
end
end
16'd68:begin
if(work_ena)begin
ad7301_channel <= ad7301_channel + 3'd1;
state <= state + 16'd1;
end
else begin
state <= 16'd0;
end
end
16'd100:begin //1.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd140:begin
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd180:begin //2.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd220:begin
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd260:begin //3.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd300:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD13
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd340:begin //4.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd380:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD12
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd420:begin //5.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd460:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD11
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd500:begin //6.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd540:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD10
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd580:begin //7.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd620:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD09
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd660:begin //8.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd700:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD08
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd740:begin //9.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd780:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD07
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd820:begin //10.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd860:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD06
SCLK <= 1'b1;
state <= state + 16'd1;
end 16'd900:begin //11.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd940:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD05
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd980:begin //12.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd1020:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD04
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd1060:begin //13.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd1100:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD03
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd1140:begin //14.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd1180:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD02
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd1220:begin //15.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd1260:begin
ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD01
SCLK <= 1'b1;
state <= state + 16'd1;
end
16'd1300:begin //16.
SCLK <= 1'b0;
state <= state + 16'd1;
end
16'd1340:begin
SCLK <= 1'b1;
ad7301_data_buf <= {ad7301_channel[2:0],(ad7301_data_buf[12:0])};
state <= state + 16'd1;
end
16'd1400:begin
ad7301_data <= ad7301_data_buf;
state <= state + 16'd1;
end
16'd1420:begin
fifo_write <= 1'b1;
state <= state + 16'd1;
end
16'd1500:begin
fifo_write <= 1'b0;
ad7301_data <= 16'd0;
state <= state + 16'd1;
end
default:begin
state <= state + 16'd1;
end
endcase
end
end
end
endmodule
/*
開始
等待1us 66次計數
給出cs，也就是8個通道其中的一個，等待34次計數
1.給出sclk低電平，等待40個周期
給出SCLK高電平，等待40個周期
2.給出sclk低電平，等待40個周期
給出SCLK高電平，等待40個周期
3.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
4.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
5.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
6.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
7.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
8.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
9.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
10.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
11.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
12.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
13.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
14.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
15.給出sclk低電平，等待40個周期
給出SCLK高電平，讀取最高位數據，等待40個周期
16.給出sclk低電平，等待40個周期
給出SCLK高電平，等待40個周期
收回CS
*/
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