/*===============================================================================================*/
/*416陳利彬編制                                                                                  */
/*修改于11月21日13：29                                                                           */
/*需要修改讀空信號，原來讀空信號是低有效，現在是高表示讀空                                       */
/*===============================================================================================*/
module core(
		RHF_ONE_,   //422 channel one half full
		RFE_ONE_,                  //422第一路fifo讀空
		RD_FIFO_ONE,               //讀422第一路fifo控制信號
		RHF_TWO_,                  //422第一路fifo半滿
		RFE_TWO_,                  //422第二路fifo讀空
		RD_FIFO_TWO,               //讀422第二路fifo控制信號
		RHF_THREE_,                //422第二路fifo半滿
		RFE_THREE_,
		RD_FIFO_THREE,
		RHF_FORE_,
		RFE_FORE_,
		RD_FIFO_FORE,
		RHF_232_,
		RFE_232_,
		RD_FIFO_232,
		/////////////////////////////////////////////
		CLK,
		reset_,
		busy_flag,
		////////////////////////////////////////////
		write_allow,
		write_bkfifo,
        ///////////////////////////////////////////
        operate_state,
        dma_finish_flag,//DMA結束標志，LA寫入該標志，表示此次DMA結束，清零地址寄存器
        current_state,
        RAM_WRITE_ADDR_POINTER,//輸出給PCI總線的地址計數器的數值
		RAM_READ_ADDR_POINTER,
        data_to_ram_en,//如果各路fifo輸出給ram的信號有效，則此位=1；否則此位==0
		data_to_fifo_en,
        RAM_ADDR,
        RAM_OE_,
        RAM_CE1_,
        RAM_CE2,
        RAM_BHE_,
        RAM_BLE_,
        RAM_WE_,
		fifo_sel,
		read_state
);

input CLK;
input reset_;
input dma_finish_flag;
//422 and 232 FIFO控制和狀態信號
input RHF_ONE_;                    //422第一路fifo半滿
input RFE_ONE_;                    //422第一路fifo讀空
output RD_FIFO_ONE;                //讀422第一路fifo控制信號
reg RD_FIFO_ONE;

input RHF_TWO_;
input RFE_TWO_;
output RD_FIFO_TWO;
reg RD_FIFO_TWO;

input RHF_THREE_;
input RFE_THREE_;
output RD_FIFO_THREE;
reg RD_FIFO_THREE;

input RHF_FORE_;
input RFE_FORE_;
output RD_FIFO_FORE;
reg RD_FIFO_FORE;

input RHF_232_;
input RFE_232_;
output RD_FIFO_232;
reg RD_FIFO_232;

//RAM的控制信號
output RAM_CE1_;
output RAM_CE2;
output RAM_BHE_;
output RAM_BLE_;
output RAM_WE_;
output [19:0] RAM_ADDR;              //20bit width
reg RAM_CE1_;
reg RAM_CE2;
reg RAM_BHE_;
reg RAM_BLE_;
reg RAM_WE_;
reg [19:0] RAM_ADDR;              //20bit width
//===================================
output RAM_OE_;
reg RAM_OE_;
//===================================
//輸出數據有效的標志
output data_to_ram_en;
reg data_to_ram_en;
output data_to_fifo_en;
reg data_to_fifo_en;
/////////////////////////////////////////////// 
reg [6:0] state;//bit 7 width
//繁忙標志信號，表示總線正在被占用
reg busy_flag;
output busy_flag;
/////////////////////////////////////

//地址計數器,用于地址對LD輸出
reg [19:0] RAM_WRITE_ADDR_POINTER;
output [19:0] RAM_WRITE_ADDR_POINTER;
//讀地址計數器，用于標志LD的DMA方式讀到RAM的哪一個地址
reg [19:0] RAM_READ_ADDR_POINTER;
output [19:0] RAM_READ_ADDR_POINTER;
output read_state;
reg read_state;
//================================================================================================//
reg [1:0] current_state;
output [1:0] current_state;
reg [1:0] next_state;
wire half_full_state;
assign half_full_state = RHF_ONE_ && RHF_TWO_ && RHF_THREE_ && RHF_FORE_ && RHF_232_;
reg [4:0] operate_state;
output [4:0] operate_state;
//reg [1:0] operate_state_read;
/*
reg operate_state_readad1;
reg operate_state_readad2;
reg operate_state_read12io;
*/
//如果任意一路fifo半滿，則half_full_state狀態為0，表示半滿，準備開始工作
reg D422_c1_fe;
reg D422_c2_fe;
reg D422_c3_fe;
reg D422_c4_fe;
reg D232_fe;

input write_allow;
output write_bkfifo;
reg write_bkfifo;
/////////////////////////////////////
output [4:0]fifo_sel;
reg [4:0]fifo_sel;
reg [3:0]read_once_counter;
/////////////////////////////////////
always @(negedge CLK or negedge reset_)
begin//1
	if(!reset_)begin
		RAM_BHE_ <= 1'b0;        //RAM_BHE_ is enable always
		RAM_BLE_ <= 1'b0;        //RAM_BLE_ is enable always
		RAM_OE_ <= 1'b1;
		RAM_WE_ <= 1'b1;
		RAM_CE1_ <= 1'b0;                     
		RAM_CE2 <= 1'b1;
		busy_flag <= 1'b0;
		
		RAM_WRITE_ADDR_POINTER <= 20'h1;//5地址計數器初始化
		operate_state <= 5'b00000;
		RAM_ADDR <= 20'h0;
		RAM_READ_ADDR_POINTER <= 20'h1;//5地址計數器初始化
		read_state <= 1'b0;
		//ds_7864fifo_rd <= 1'b1;
		//ds_7301fifo_rd <= 1'b1;
		RD_FIFO_ONE <= 1'b0;
		RD_FIFO_TWO <= 1'b0;
		RD_FIFO_THREE <= 1'b0;
		RD_FIFO_FORE <= 1'b0;
		RD_FIFO_232 <= 1'b0;

		//operate_state_readad1 <= 1'b0;
		//operate_state_readad2 <= 1'b0;
		//operate_state_read12io <= 1'b0;
		D422_c1_fe <= 1'b1;
		D422_c2_fe <= 1'b1;
		D422_c3_fe <= 1'b1;
		D422_c4_fe <= 1'b1;
		D232_fe <= 1'b1;
		data_to_ram_en <= 1'b0; 
		data_to_fifo_en <= 1'b0;
		
		fifo_sel<=5'b11111;
		read_once_counter<=4'd0;
		write_bkfifo <= 1'b0;
	end
	else begin//2
		casex(current_state)
		3'd0:begin
			//busy_flag <= busy_flag;//沒有任何處理 busy == 0
			if(busy_flag)	begin
				case (read_state)
				1'b0:	begin
					if(!read_once_counter[3])	begin
					write_bkfifo <= 1'b0;
					RAM_OE_ <= 1'b0;
					RAM_ADDR <= RAM_READ_ADDR_POINTER;//放入地址
					RAM_READ_ADDR_POINTER <= RAM_READ_ADDR_POINTER + 20'd1;//計數器+1
					read_state <= 1'b1;
					//RAM_CE1_ <= 1'b0;                     
					//RAM_CE2 <= 1'b1;
					end
					else begin
					write_bkfifo <= 1'b0;
					busy_flag<=1'b0;
					RAM_OE_ <= 1'b1;
					//RAM_CE1_ <= 1'b1;                     
					//RAM_CE2 <= 1'b0;
					read_once_counter <= 4'd0;
					data_to_fifo_en <= 1'b0;
					end
				end
				1'b1:	begin
					write_bkfifo <= 1'b1;
					read_state <= 1'b0;
					read_once_counter <= read_once_counter+4'd1;
				end
				default:	begin
					write_bkfifo <= 1'b0;
					busy_flag<=1'b0;
					RAM_OE_ <= 1'b1;
					//RAM_CE1_ <= 1'b1;                     
					//RAM_CE2 <= 1'b0;
					read_state <= 1'b0;
				end
				endcase
			end
			else if((busy_flag==1'b0)&&(!write_allow/*FIFO有8bit空余*/)&&(RAM_READ_ADDR_POINTER<RAM_WRITE_ADDR_POINTER/*RAM的讀指針 小于 寫指針*/) )
			begin
				busy_flag <= 1'b1;
				data_to_fifo_en <= 1'b1;
			end
			else begin
				busy_flag <= 1'b0;
				data_to_fifo_en <= 1'b0;
			end
		end
		3'd1:begin//fifo半滿了，從第一路到第四路，開始一次向ram里面寫數據，然后地址自加一
			case(operate_state)
			5'd0:begin//這里應該首先加入判斷，防止只有一路422工作的bug
					busy_flag <= 1'b1;//busy == 1
					data_to_ram_en <= 1'b1;//表示模塊正在向RAM寫數據
				if(RFE_ONE_ == 1)begin//表示fifo沒有被讀空
					operate_state <= 5'd1;//進入狀態1
					RD_FIFO_ONE <= 1'b0;//收回讀fifo信號
				end
				else begin//如果fifo被讀空了
					RD_FIFO_ONE <= 1'b0;
					fifo_sel[1]<=1'b1;
					operate_state <= 5'd4;//進入狀態4
				end
			end
			5'd1:begin
				if(RFE_ONE_ == 1)begin
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+計數器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//計數器+1//eulerhit
					//RAM_CE1_ <= 1'b0;//加入寫ram控制信號3個
					//RAM_CE2 <= 1'b1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd2;