?? core.v
字號:
//*****************************
fifo_sel[1]<=1'b0;
end
else begin
RD_FIFO_ONE <= 1'b0;
fifo_sel[1]<=1'b1;
operate_state <= 5'd4;//進入狀態4
end
5'd2:begin
D422_c1_fe <= RFE_ONE_;//不過這里沒有使用到這一位標志
operate_state <= 5'd3;//進入狀態3
end
5'd3:begin
//RAM_CE1_ <= 1'b1;//拉高ram控制信號
//RAM_CE2 <= 1'b0;
RAM_WE_ <= 1'b1;
operate_state <= 5'd0;//進入狀態0
RD_FIFO_ONE <= 1'b1;//給出讀fifo信號，該信號高有效
end
//==================================================================================//
5'd4:begin//這里應該首先加入判斷，防止只有一路422工作的bug
if(RFE_TWO_ == 1)begin //如果fifo沒有被讀空
operate_state <= 5'd5;//進入狀態5
RD_FIFO_TWO <= 1'b0;
end
else begin//如果fifo被讀空了
RD_FIFO_TWO <= 1'b0;
fifo_sel[2]<=1'b1;
operate_state <= 5'd8;//進入狀態8
end
end
5'd5:begin
if(RFE_TWO_ == 1)begin //如果fifo沒有被讀空
RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+計數器
RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//計數器+1//eulerhit
//RAM_CE1_ <= 1'b0; //加入寫ram控制信號3個
//RAM_CE2 <= 1'b1;
RAM_WE_ <= 1'b0;
operate_state <= 5'd6;
//*****************************
fifo_sel[2]<=1'b0;
end
else begin//如果fifo被讀空了
RD_FIFO_TWO <= 1'b0;
fifo_sel[2]<=1'b1;
operate_state <= 5'd8;//進入狀態8
end
end
5'd6:begin
D422_c2_fe <= RFE_TWO_;
operate_state <= 5'd7;//進入狀態7
end
5'd7:begin
//RAM_CE1_ <= 1'b1; //拉高ram控制信號
//RAM_CE2 <= 1'b0;
RAM_WE_ <= 1'b1;
operate_state <= 5'd4;//進入狀態4
RD_FIFO_TWO <= 1'b1;//給出讀fifo信號
end
//==================================================================================//
if(RFE_THREE_ == 1)begin //如果fifo沒有被讀空
operate_state <= 5'd9;//進入狀態9
RD_FIFO_THREE <= 1'b0; //收回讀fifo信號
end
else begin//如果fifo被讀空了
RD_FIFO_THREE <= 1'b0;
fifo_sel[3]<=1'b1;
operate_state <= 5'd12;//進入狀態12
end
end
5'd9:begin
if(RFE_THREE_ == 1) begin
RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+計數器
RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//計數器+1//eulerhit
//RAM_CE1_ <= 1'b0; //加入寫ram控制信號3個
//RAM_CE2 <= 1'b1;
RAM_WE_ <= 1'b0;
operate_state <= 5'd10;//進入狀態10 //這里fifo數據輸出端直接連接到ram數據總線上
//*****************************
fifo_sel[3]<=1'b0;
end
else begin
RD_FIFO_THREE <= 1'b0;
operate_state <= 5'd12;//進入狀態12
fifo_sel[3]<=1'b1;
end
end
5'd10:begin
D422_c3_fe <= RFE_THREE_;
operate_state <= 5'd11;//進入狀態11
end
5'd11:begin
//RAM_CE1_ <= 1'b1; //拉高ram控制信號
//RAM_CE2 <= 1'b0;
RAM_WE_ <= 1'b1;
operate_state <= 5'd8;//進入狀態8
RD_FIFO_THREE <= 1'b1;//給出讀fifo信號
end
//==================================================================================//
5'd12:begin
if(RFE_FORE_ == 1)begin //如果fifo沒有被讀空
operate_state <= 5'd13;//進入狀態13
RD_FIFO_FORE <= 1'b0; //收回讀fifo信號
end
else begin//如果fifo被讀空了
RD_FIFO_FORE <= 1'b0;
fifo_sel[4]<=1'b1;
operate_state <= 5'd16;//進入狀態16
end
end
5'd13:begin
if(RFE_FORE_ == 1)begin
RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+計數器
RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//計數器+1//eulerhit
//RAM_CE1_ <= 1'b0; //加入寫ram控制信號3個
//RAM_CE2 <= 1'b1;
RAM_WE_ <= 1'b0;
operate_state <= 5'd14;//進入狀態14
//*****************************
fifo_sel[4]<=1'b0;
end
else begin
RD_FIFO_FORE <= 1'b0;
fifo_sel[4]<=1'b1;
operate_state <= 5'd16;
end
end
5'd14:begin
D422_c4_fe <= RFE_FORE_;
operate_state <= 5'd15;//進入狀態15
end
5'd15:begin
//RAM_CE1_ <= 1'b1; //拉高ram控制信號
//RAM_CE2 <= 1'b0;
RAM_WE_ <= 1'b1;
operate_state <= 5'd12;//進入狀態12
RD_FIFO_FORE <= 1'b1;//給出讀fifo信號
end
//==================================================================================//
5'd16:begin
if(RFE_232_ == 1)begin //如果fifo沒有被讀空
operate_state <= 5'd17;//進入狀態17
RD_FIFO_232 <= 1'b0; //收回讀fifo信號
end
else begin//如果fifo被讀空了
fifo_sel[0]<=1'b1;
data_to_ram_en <= 1'b0;//表示模塊向RAM寫數據完畢
operate_state <= 5'd20;//進入狀態16
end
end
5'd17:begin
if(RFE_232_ == 1)begin
RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+計數器
RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//計數器+1//eulerhit
//RAM_CE1_ <= 1'b0; //加入寫ram控制信號3個
//RAM_CE2 <= 1'b1;
RAM_WE_ <= 1'b0;
operate_state <= 5'd18;//進入狀態18
//*****************************
fifo_sel[0]<=1'b0;
end
else begin
data_to_ram_en <= 1'b0;
fifo_sel[0]<=1'b1;
operate_state <= 5'd20;
end
end
5'd18:begin
D232_fe <= RFE_232_;
operate_state <= 5'd19;//進入狀態19
end
5'd19:begin
//RAM_CE1_ <= 1'b1; //拉高ram控制信號
//RAM_CE2 <= 1'b0;
RAM_WE_ <= 1'b1;
RD_FIFO_232 <= 1'b1;//給出讀fifo信號
operate_state <= 5'd16;//進入狀態16
end
default:begin
data_to_ram_en <= 1'b0;//表示模塊向RAM寫數據完畢
busy_flag <= 1'b0;
RAM_WE_ <= 1'b1;
RD_FIFO_ONE <= 1'b0; //收回讀fifo信號
RD_FIFO_TWO <= 1'b0; //收回讀fifo信號
RD_FIFO_THREE <= 1'b0; //收回讀fifo信號
RD_FIFO_FORE <= 1'b0; //收回讀fifo信號
RD_FIFO_232 <= 1'b0; //收回讀fifo信號
end
endcase
end
endcase
end//2
end//1
//====================================================================================================//
always @ (*)
begin
if( ((half_full_state == 0) && (busy_flag == 0)) || ((timer_start_flag == 1) && (busy_flag == 0)) ) begin
next_state = 2'd1;//如果任意一路422半滿并且busy==0，或者定時器計數到5ms并且busy==0，則觸發下一狀態==1
end
else
begin
if(busy_flag == 0) begin
next_state = 2'd0;
end
else begin
next_state = current_state;
end
end
end
//====================================================================================================//
//狀態轉換，將下一狀態賦值給當前狀態
always @(posedge CLK)
begin
current_state <= next_state;
end
//====================================================================================================//
//定時器計數器
reg timer_start_flag;//定時器有效標志，當這一位有效，表示定時器計數到5ms，開始查詢，高有效，低無效
parameter time_delay = 20'b10_0100_1111_1101_1011;//20'd151515 time = 151515*33ns = 4.999995ms
reg [19:0] timer;
always @ (posedge CLK or negedge reset_)
if (!reset_)begin
timer <= 20'b0;
timer_start_flag <= 1'b0;
end
else begin
if(timer <= time_delay - 20'd1)begin
timer <= timer + 20'b1;
end
else if(timer <= time_delay + 20'd1) begin
if(busy_flag == 1'b1)begin//如果busy==1，表示正在工作，則如果計數器達到計數時間，則需要延遲數個周期
timer <= timer;
timer_start_flag <= 1'b1;
end
else begin
timer <= timer + 20'b1;
timer_start_flag <= 1'b1;
end
end
else begin
timer <= 20'd0;
timer_start_flag <= 1'b0;
end
end
//==================================================================================//
endmodule
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